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In the rapidly advancing field of artificial intelligence, two neural network architectures have become prominent: convolutional neural networks (CNNs) and transformers. Each architecture has brought significant advancements to various domains, ranging from image recognition, video surveillance to natural language processing (NLP), speech recognition and generation, multimodal AI and more. This article aims to compare…

Data rates are escalating with seemingly no end in sight due to the insatiable demand for more bandwidth to accommodate AI factories and other data-intensive AI/ML, HPC, cloud, and data center applications. As just one example, the new PCI Express (PCIe) 7.0 specification doubles the bandwidth over its predecessor—boasting a raw bit rate of 128.0 GT/s for a maximum bandwidth of 512 GB/s bidirectionally in a 16-lane configuration…

For ages, Ethernet has been the backbone of networking — starting from simple web browsing to cloud computing, data centers, automobiles, and more. Ethernet has enabled countless innovations, and now, it's expanding to meet the demands of AI and HPC.

As the world shifts toward these new technologies, new challenges are emerging. These include increased scale, higher bandwidth density, multi-pathing, and fast…

In the intricate world of digital design, timing is everything. At the heart of this precision lies clock tree synthesis (CTS)—a critical step in the physical design flow that ensures clock signals reach all sequential elements with minimal skew and optimal latency. Whether you're a seasoned engineer or a curious learner, understanding CTS is essential for achieving robust, high-performance silicon.

As chip…

Welcome to the binge-worthy series you didn't know you needed—"EDA: Silicon, Security and Shenanigans." Whether you're a chip whisperer or just here for the memes, these videos will take you from sand to silicon with more plot twists than your favorite series—and yes, the transistors have feelings, too (almost).

Designed for anyone—from engineers to educators—who's ever been fascinated by…

In the fast-paced world of digital design and verification, simulation tools are the backbone of robust, error-free development. Among the industry leaders, the Cadence Xcelium Logic Simulator stands out for its performance, flexibility, and comprehensive debugging capabilities. Whether you're a verification engineer, a digital designer, or a systems integrator, mastering the Xcelium simulator can significantly boost…

The demands of modern cloud computing—massive scale, constant agility, and tight security—are pushing traditional I/O virtualization to its limits. While SR-IOV (Single Root I/O Virtualization) was a foundational technology, it wasn't built for the high-density, multi-tenant environments common today.

To meet this challenge, the PCIe specification has evolved with Scalable I/O Virtualization (SIOV), a…

FMS: the Future of Memory and Storage is fast approaching (August 5-7 at the Santa Clara Convention Center), and with it comes a unique opportunity to connect with some of the brightest minds in the semiconductor, memory, and storage industry. This premier event brings together industry experts, innovators, and leaders to highlight advancements shaping the future of memory and storage technology.

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market today where it’s used in a diverse set of applications that spans mobile/handheld devices, IoT, client and server, automotive, virtual reality/gaming consoles, robotics, data centers, and AI applications, just to name a few.

JEDEC has just released the LPDDR6 specification that is expected to take the LPDDR DRAM market…

As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become the backbone of modern data centers, they generate and consume a massive amount of data. Traditional Ethernet was not built for such high-bandwidth traffic.

In HPCs and AI models, computations are distributed across the nodes and the data is shared in real time with low latency and lossless communication. As all the processes are synchronized…

High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.

MPHY serves as the physical layer for the MIPI UniPro transport layer. The MPHY+UniPro stack is used with the JEDEC-defined UFS application…

Low-power DDR SDRAM is one of the most widely used memories in the semiconductor market today. It's used in a diverse set of applications that span mobile/handheld devices, IoT, client and server, automotive, virtual reality/gaming consoles, robotics, data centers, and AI applications, just to name a few.

For over 50 years, JEDEC has been the global leader in developing open standards for the microelectronics industry…

Power planning in chip design is a lot like managing your monthly budget. If you don't keep an eye on where the watts are going, you might end up with a chip that's all flash and no efficiency—kind of like spending your entire salary on gadgets and forgetting about rent. You'll end up with a chip that's overdrawn on power and deep in thermal debt.

 Believe it or not—chips hate overdraft fees, too…

The rapid evolution of artificial intelligence (AI) is reshaping the technological landscape, driving unprecedented demands on computing infrastructure. At the heart of this transformation lie innovations in intellectual property (IP) that enable scalable, efficient, and performance-driven AI factories. These advancements are central to addressing the technical challenges of modern AI workloads while ensuring adaptability…