Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Analog/Custom Design: Virtuoso Video Diary: The SKILLed Way of Using Plotting Templates

Udit Rajput

Read through this blog to know more about how to use the maeGetAllPlottingTemplates, maePlotWithPlottingTemplate, and maeSaveImagesUsingPlottingTemplate SKILL functions to work with maestro plotting templates.
- 20 Aug 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: How to Run a RAVEL Rule from the GUI

Shreyansh

With the current scenario of COVID-19, you cannot do without rules. You have to soak vegetables in brine for ten minutes, wash milk in plastic packaging with soap, sanitize metals with an alcoholic solution (70% and above), and whatnot. Well, you get...
- 19 Aug 2020
Breakfast Bytes: Thermal Analysis of Protium X1

Paul McLellan

There's a phrase in software development "eat your own dogfood". In fact, there's even an ugly verb "dogfooding". This means using your own software for real. If, say, you are developing a source-code management system (al...
- 19 Aug 2020
Analog/Custom Design: Virtuoso IC6.1.8 ISR13 and ICADVM18.1 ISR13 Now Available

Virtuoso Release Team

The IC6.1.8 ISR13 and ICADVM18.1 ISR13 production releases are now available for download.
- 19 Aug 2020
System, PCB, & Package Design : IC Packagers: Designing a Package from the Flip-Chip’s Perspective

Tyler

Most package substrates are designed as they will be placed onto the host PCB if the package were mounted on the top side. This means that the BGA’s balls are on the bottom layer of the cross-section. Your dies are mounted on the top. For wire ...
- 18 Aug 2020
Breakfast Bytes: Climbing Annapurna to the Clouds

Paul McLellan

One of the keynotes at last week's CadenceLIVE Americas 2020 was by Nafea Bshara. He is a VP/Distinguished Engineer at Amazon, working on system/hardware/silicon products for AWS infrastructure. But perhaps more importantly, he joined AWS in 2016 whe...
- 18 Aug 2020
カスタムIC／ミックスシグナル: Virtuosity: 古いADEのstateやviewをADE ExplorerまたはADE Assemblerで開く

Custom IC Japan

Virtuoso ® ADE L stateやVirtuoso ® ADE XL viewを開くとき、デフォルトのアプリケーションが、以前の古いADE LまたはXLにセットされていることが面倒だと感じた事はありませんか？すでにVirtuoso ® ADE AssemblerやVirtuoso ® ADE Explorerに移行済みである場合、Open Fileダイアログで指定されているアプリケーションをADE ExplorerやADE As...
- 17 Aug 2020
Breakfast Bytes: Alberto's Keynote: Cadence and Academia

Paul McLellan

On the last day of CadenceLIVE 2020, there was a keynote by Alberto Sangiovanni-Vincentelli. Just in case it wasn't obvious from his name that he's Italian, he delivered the keynote from his villa on the Mediterranean coast near Rome. He titl...
- 17 Aug 2020
定制IC芯片设计 : Virtuoso Meets Maxwell: Bumps, Bumps……如何找到Bumps？

Brian LaBorde

Bumps对Virtuoso MultiTech Framework解决方案来说至关重要, 它提供了堆叠芯片，中介层，封装和电路板两两间的连接。 Bump的位置，连接性和其他属性都是创建TILP的基础，我们将这些属性结合以生成系统级版图。 ”Virtuoso Meets Maxwell “是一系列旨在探讨Virtuoso RF 和Virtuoso MultiTech现有及潜在功能的博客。Virtuoso又是如何与麦克斯韦方程组(Maxwell)联系上的呢? 当前版本的Virtuoso 支持射频设计，设计工程师们使用麦克斯韦方程组，就能测量物理和辐射效应。该系列博客除了提供一些实用软件和增强功能的精辟见解外，还能通过播客的方式，与听众分享博主和专家们在使用Virtuoso Pack...
- 16 Aug 2020
Breakfast Bytes: Sunday Brunch Video for 16th August 2020

Paul McLellan

https://youtu.be/7W55PNo-SoI Made in "CadenceLIVE Lounge" (camera me) Monday: 120th Anniversary of Hilbert's Problems Tuesday: Cadence Executives on Computational Software Wednesday: Xcelium ML: Black-Belt Verification Enginee...
- 16 Aug 2020
Analog/Custom Design: Start Your Engines: Pointers to Speed Up a Slow Mixed-Signal Simulation

Lalit Mohan

There may be times when the mixed-signal verification engineers observe a slow analog mixed-signal (AMS) simulation. The complexity of design and inappropriate usage of simulator options may be the causes of this slowness.
- 14 Aug 2020
Breakfast Bytes: CadenceLIVE 2020: As It Happened

Paul McLellan

CadenceLIVE 2020 Americas took place virtually earlier this week, spread across Tuesday, Wednesday, and Thursday. First, there were close to 2,000 attendees. Since this was a virtual conference, it's not fair to compare that number to last year ...
- 14 Aug 2020
Analog/Custom Design: Virtuosity: In the Line of Veri-Fire - Episode 4

Team ADE Verifier

Want to know what's new in this episode of Veri-Fire? Check it out!
- 13 Aug 2020
Breakfast Bytes: Computational Logistics

Paul McLellan

General Omar Bradley famously said: “Amateurs talk strategy. Professionals talk logistics.” And Napoleon (perhaps) said "An army marches on its stomach". That's not to underestimate other aspects of armies, such as...
- 13 Aug 2020
Academic Network: Custom IC, Analog, and RF Design Training Deep Dive: Part 3

Kira Jones

Welcome to part 3 of the Custom IC, Analog, and RF Design Online Training deep dive blog series. Part 3 will be building off the skills learned in Part 1 and Part 2 so be sure that you are familiar with those tools and technologies before beginning t...
- 12 Aug 2020
Breakfast Bytes: Xcelium ML: Black-Belt Verification Engineer in a Tool

Paul McLellan

What if I told you I knew someone who could improve your regression efficiency: make fewer runs, spend less runtime on the runs you do make, and have the same coverage at the end? You'd say that he or she sounds like a great verification e...
- 12 Aug 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Magic! – Dynamic Voiding in Virtuoso RF Solution

skai

While SiP Layout Option is – and continues to be – one of the most complete solutions for package design, the Virtuoso RF Solution gives access to a constantly increasing set of package layout authoring capabilities inside the Virtuoso Layout Suite. Having both IC and package inside the same design platform enables Virtuoso users to do package layout in their preferred design environment. An innovative co-design environment…
- 11 Aug 2020
System, PCB, & Package Design : BoardSurfers: Allegro In-Design Crosstalk Analysis: Signal Integrity Simulations on the PCB Canvas

Shirin Farrahi

Crosstalk is the transfer of unwanted signals from an “aggressor” net to a “victim” and is one of the major classes of signal integrity (SI) problems that can exist in Printed Circuit Board (PCB) designs. Reducing crosstalk as...
- 11 Aug 2020
System, PCB, & Package Design : IC Packagers: Make Acute Angles a Sharp Problem of the Past

Tyler

Sharp angles, whether they create a spike in a poured shape or form an acid trap between two different pieces of metal, are a problem for us all. And as designers, we will go out of our way to try and avoid creating these situations; they will still ...
- 11 Aug 2020
Breakfast Bytes: Cadence Executives on Computational Software

Paul McLellan

CadenceLIVE starts today, Tuesday, August 11, and runs through Thursday. One thing that I know some of the keynotes will cover will be computational software, a name for many of the sorts of algorithms that underlie EDA and system design tools....
- 11 Aug 2020
カスタムIC／ミックスシグナル: Virtuosity: Multi-Technology Simulation (MTS)の実行方法は？

Custom IC Japan

マルチ・テクノロジ・シミュレーション(Multi-Technology Simulation; MTS)をVirtuoso® ADE ExplorerとVirtuoso® ADE Assemblerで実行する方法を示したハンズオン型の資料をお探しですか？今日の急速にシュリンクしているテクノロジでは、カスタムICシステム・イン・パッケージ(System-in-Package; SiP)を設計する機会が増えています。しかし、ここで課題となるのが、異なるテクノロジを使用してこれらの...
- 11 Aug 2020
Digital Design: Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric Protection Scheme

Vijetha

This blog highlights the key capabilities and benefits of the Voltus ESD analysis flow.
- 10 Aug 2020
Breakfast Bytes: 120th Anniversary of Hilbert's Problems

Paul McLellan

The computational software algorithms used in EDA are fundamentally mathematical in nature. Many algorithms are various forms of computation using very large sparse matrices. Last Saturday was a significant anniversary in the foundations of mathemati...
- 10 Aug 2020
PCB、IC封装：设计与仿真分析: 电子系统设计中进行片上热分析的四大挑战与应对

SDA China

在大约 138 亿年前的创生之初，我们的宇宙在 0 到 10-43 (10^(-43))秒的短短时间里产生和释放了大量的热量或能量，这在理论上得到了各种模型和测量数据的支持。自那以后，宇宙中各种各样的物理机制一直推动着能量不断转化为其他形式或者转化回热量，大到太阳中的核聚变，小到电子设备中计算机芯片上微型晶体管的自发热。而为了让每个系统都运行良好，无论是像病毒一样的活体，还是像智能手机一样的人造设备，工作温度范围都是与系统敏捷性息息相关的最重要因素之一。因此，在能量输入和输出的各种预期条件下，能...
- 9 Aug 2020
Breakfast Bytes: Weekend Update 2

Paul McLellan

This is my second update post where I cover things that I have covered before, and where there is some news, but no enough to make a completely new post. The first update was Weekend Update. Cerebras Wafer Scale Engine I wrote about the Cerebras Wafe...
- 7 Aug 2020

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.