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Breakfast Bytes: The Rosetta Stone and the British Museum

Paul McLellan

In the first week of January, I wrote about Lars Liebmann's Rosetta Stone of Lithography in two posts The History of Lithography, Part 1: From Stones to Lasers and The History of Lithography, Part 2: From Double-Patterning to EUV. Today, the...
- 10 Jan 2020
Breakfast Bytes: What's New in Consumer Electronics? CES 2020

Paul McLellan

I come to Las Vegas in the first week of January each year to attend what used to be called the Consumer Electronics Show but now is officially just its initials CES. Over 175,000 attendees are expected. The first pleasant surprise was that they had ...
- 9 Jan 2020
Breakfast Bytes: The 40th Anniversary of LAMBDA Magazine

Paul McLellan

Forty years ago today, January 8, 1980, the first issue of LAMBDA magazine was published. The Mead & Conway revolution was getting underway. Doug Fairbairn was at Xerox PARC with Lynn Conway. He would go on to be one of the founders of VLSI ...
- 8 Jan 2020
System, PCB, & Package Design : IC Packagers: Four Reasons to Avoid Multi-Layer Flip-Chip Pin Padstacks

Tyler

Designing a package substrate, there are things that many of us do that perhaps we should think twice about. One of those being using a multi-layer padstack for the pins of flip-chip dies. I understand the attractiveness of doing this, but if you’ll give me just a few moments, perhaps I can convince you to put ...
- 7 Jan 2020
System, PCB, & Package Design : BoardSurfers: PCB Electronics—Six Tasks to Prepare Board for Manufacturing

mrigashira

You have placed components and routed the board. You are finally ready to send the design to a fabrication house to be manufactured. But wait, you have to perform a few tasks ...
- 7 Jan 2020
Breakfast Bytes: Open Source in 2020

Paul McLellan

I recently wrote a couple of posts about open-source EDA tools, OpenROAD: Open-Source EDA from RTL to GDSII and 2nd WOSET Workshop on Open-Source EDA. I have also written about open-source in general, as an approach to development and an ap...
- 7 Jan 2020
Breakfast Bytes: Protium and Palladium 1st=

Paul McLellan

We just finished 2019, of course, so it is time for annual "Best of 2019" lists. Over at John Cooley's DeepChip there was a tie at #1...between the Protium X1 platform and the Palladium Z1 platform. I said that the winners were Protium ...
- 6 Jan 2020
Breakfast Bytes: The History of Lithography, Part 2: From Double-Patterning to EUV

Paul McLellan

This is a continuation of yesterday's post The History of Lithography, Part 1: From Stones to Lasers. I'm going to drop in a copy of Lars Liebmann's Rosetta Stone of Lithography so you have it in this post, too. If you want more of an expla...
- 3 Jan 2020
Breakfast Bytes: The History of Lithography, Part 1: From Stones to Lasers

Paul McLellan

Lithography was originally a way of printing using a flat stone. Lithos (or λίθος) is the Greek for stone. The stone would be coated with wax, then a drawing made in the wax with some sort of stylus. You had to use a ...
- 2 Jan 2020
The India Circuit: 2019: The Year That Was...And Some Surprising News

Madhavi Rao

The biggest happening in 2019 for India was, of course, the general elections. (Though some may argue that it was the ICC Cricket World Cup, which happens every four years!). While uncertainty and instability were prevalent across the world in 2019, ...
- 31 Dec 2019
System, PCB, & Package Design : The Year That Was: PCB Design Blogs in 2019

Monika

The first series BoardSurfers is about PCB designing. It provides information on concepts, techniques, and processes that are related to Cadence PCB Design solutions with a new post published ...
- 31 Dec 2019
System, PCB, & Package Design : IC Packagers: Stepping into 2020

mrigashira

We started 2019 with the promise to cover all the topics that might interest you as we go, looking at a new area every week. To keep this promise we had a whole lot of exciting tasks. To start with we needed to know what you want to re...
- 30 Dec 2019
System, PCB, & Package Design : IC Packagers: Routing Clean-Up Prior to Manufacturing

Tyler

A fantastic year is ending, so I want to take a quick opportunity to go over some of the lesser-known commands available to you for cleaning up and optimizing your routing for manufact...
- 29 Dec 2019
System, PCB, & Package Design : IC Packagers: Guiding Your Team with Workflows

Tyler

The flow for efficiently and correctly designing a package substrate layout is a complex task. Many teams define steps to be followed by designers to make sure that rul...
- 24 Dec 2019
Breakfast Bytes: Sunday Brunch Video for 22nd December 2019

Paul McLellan

https://youtu.be/iEuzyt_6O_A Made in my living room (camera Carey Guo) Monday: The Most Important Operating System Ever Tuesday: What's Happening in RISC-V Land? Wednesday: System in Package? How to Plan and Build It Thursday: IEDM 2019...
- 22 Dec 2019
PCB、IC封装：设计与仿真分析: 如何利用Allegro SiP Layout工具5步实现复杂引线框架封装的完整设计？

TeamAllegro

文章翻译自Cadence博客“Designing a Complex Leadframe Package? See How SiP Layout Tool Can Cover All the Steps”。 space 随着技术的发展，引线框架封装设计变得越来越复杂。新材料和制造工艺的出现，使得封装中可以有更多有源和无源元件，同时新的接合能力扩展了可用引脚数量。与此同时，信号完整性、电源完整性和温度完整性挑战也随之增加。以前可以在机械CAD工具中完成的简单设计，现在需要...
- 20 Dec 2019
Academic Network: Cadence Co-organized the First EDA Competition to Help China Train More EDA Talent

Tracy Zhu

The first “China IC and EDA Design Elite Competition” started in June 2019 and received high attention and support from many universities. In total, there&nbs...
- 20 Dec 2019
Breakfast Bytes: Off-Topic: 2019 TV Anniversaries

Paul McLellan

It's the day before a holiday. Or in this case, ten days when Cadence will be shut down. As is traditional, I write about whatever I feel like, provided it has nothing to do with EDA or semiconductors. Today, some TV programs. This has been a big yea...
- 20 Dec 2019
Digital Design: Library Characterization Tidbits: A Matrix for Your Reference

Jommy

When working on multiple tools of the Cadence Liberate Characterization Portfolio, do you tend to get confused about which commands or parameters are supported in a specific tool? Read more...
- 19 Dec 2019
Breakfast Bytes: IEDM 2019: An Overview...Plus the Future of EUV

Paul McLellan

IEDM, the International Electron Devices Meeting, took place last week. It was also the RISC-V Summit that week, so I missed most of Tuesday at IEDM since I went down to San Jose. My overview of the RISC-V Summit is in a post earlier in the week What...
- 19 Dec 2019
Analog/Custom Design: Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization and Analysis in 2019

shubhangi upadhyay

2019 was quite an eventful year for Virtuoso ADE Product Suite and Virtuoso Visualization and Analysis XL. We not only added new features such as Multi-Test Editor, but also redesigned existing forms to give you the best possible experience with the existing features.
- 19 Dec 2019
Digital Design: 2019 Annual HLS Survey Results

dpursley

Each year, we survey the industry to get an idea of the industry’s experiences and expectations of high-level synthesis (HLS). As in last year’s survey, approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on productivity.

Spoiler alert: Users find the HLS flow to be over 2.5x more productive for design and nearly 4x more…
- 18 Dec 2019
Breakfast Bytes: System in Package? How to Plan and Build It

Paul McLellan

This is a follow on to my previous two pieces about system-in-package (SiP) designs, System in Package, Why Now? Part 1 and Part 2. I'm going to use the term SiP generically just to mean any design with more than one die in the package. The focu...
- 18 Dec 2019
System, PCB, & Package Design : BoardSurfers: Four Reasons to Use Allegro ECAD-MCAD Library Creator

Sanjiv Bhatia

The Cadence Allegro ECAD-MCAD Library Creator helps you easily synchronize ECAD and MCAD libraries which in turn improves the quality and accuracy ....
- 17 Dec 2019
System, PCB, & Package Design : IC Packagers: An Introduction to Allegro Package Designer Plus in 17.4

Tyler

Some of you are APD users, building single-chip or non-stacked multi-chip packages. Others of you are SiP Layout XL users, probably stacking dies or embedding elemen...
- 17 Dec 2019

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