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System, PCB, & Package Design : IC Packagers: Expanding Your (Thermal) Repertoire

Tyler

The process of attaching a component to your package substrate involves many factors, including heat. What happens whenever heat is applied to something? Expansion, of course! How much your die expands during the assembly process will be influenced b...
- 21 May 2019
Breakfast Bytes: Samsung's 3nm GAA Process

Paul McLellan

At the recent Samsung Foundry Forum, HK Kang, the EVP of semiconductor R&D, took to the stage. He's in charge of advanced logic, DRAM, 3D NAND, mask. But that day he was just going to talk about Samsung's 3nm gate-all-around (GAA) technol...
- 21 May 2019
Breakfast Bytes: Alberto and the Origins of the EDA Industry

Paul McLellan

At the 2019 International Symposium of Physical Design, the conference honored Alberto Sangiovanni-Vincentelli with a lifetime achievement award. Alberto was one of the cofounders of SDA Systems, the forerunner of Cadence, so in some ways he's a foun...
- 20 May 2019
Breakfast Bytes: Sunday Brunch Video for 19th May 2019

Paul McLellan

https://youtu.be/cTEPUNpqcRg Made at Samsung HQ (camera Sean) Monday: Bob Smith on ESD Alliance, ES Design West...with Wine Tuesday: After Meltdown and Spectre Wednesday: Vision Q7 DSP: Real-Time Vision and AI at the Edge Thursday: Samsung ...
- 19 May 2019
PCB、IC封装：设计与仿真分析: 汽车以太网应用的SI分析技术

Sigrity

现今汽车中车载电子设备的爆炸式增长，正在迅速改变向汽车消费者圆满提供高性能、可靠功能所需的工具和方法。汽车印刷电路板（PCB）的设计传统上一直由几个简单的器件互连组成、使用2层PCB，主要考虑的是成本问题。但是随着先进驾驶员辅助系统（ADAS）的普及，现在汽车可以包含多达100个电子控制模块（ECU），通过多线缆电缆束与安装在汽车四周的传感器相连。为适应传感器、数字逻辑与ECU之间更高性能的传输，汽车中所用部件之间的信号传输也在发生变化。目前大多数汽车采用的设计标准是100BASE-T1网络...
- 17 May 2019
Academic Network: CDNLive EMEA 2019, Impressions from the Academic Track

Anton Klotz

CDNLive EMEA 2019 was held May 6-8 in Munich, Germany. Bayern Munich did not qualify for the Champions League this year, so we were completely undisturbed and could listen to presentations, visit the exhibition, explore new ideas on collaboration and...
- 17 May 2019
Breakfast Bytes: Top 10 Reasons to Go to DAC

Paul McLellan

The Design Automation Conference is coming up soon. It's in Las Vegas from June 2 to 6 in the Las Vegas Convention Center (LVCC). Rob Aitken I was putting together a post on what I thought were good reasons to attend, but I decided to c...
- 17 May 2019
System, PCB, & Package Design : IC Packagers: Create Daisy Chain Substrates in a Flash with Cadence SiP Layout

Tyler

How do you go about testing your IC or package substrate when it comes to physical endurance? For many of us, a daisy chain test package is a common option. With practical uses including extreme environmental and temperature testing scenarios, a dais...
- 16 May 2019
Analog/Custom Design: Virtuoso Video Diary: The Next Big Thing — ADE Verifier Teams Up with Cadence vManager

Rashmi G

Need to perform functional verification of a mixed-signal design? Using the connection between Verifier and vManager, analog and digital engineers get to work together with two different tools using the same data. A single view allows a project manager to look up all the results together and the engineers to sign off the project. You have fulfilled traceability and tracking of results for internationally acknowledged…
- 16 May 2019
Breakfast Bytes: Samsung Process Roadmaps

Paul McLellan

Recently, Samsung held the third Samsung Foundry Forum (SFF) at the Marriott in Santa Clara. They had so many attendees that they pretty much overflowed the biggest ballroom in the hotel and had to set up a temporary structure in the parking lot for ...
- 16 May 2019
SoC and IP: Designing for the Future - Managing the Impact of Moore's Law

TomWong

With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage improvements in process technology to get performance improvements for many years now. Let’s examine whether or not this assumption is still valid.

When we were at more mature technologies, such as 90nm to 65nm, there…
- 15 May 2019
Breakfast Bytes: Vision Q7 DSP: Real-Time Vision and AI at the Edge

Paul McLellan

At CDNLive EMEA, we announced the latest member of the Tensilica family at the press conference, although it was embargoed until this morning. This is the Tensilica Vision Q7 DSP. The earliest Vision cores were purely focused on image processing in t...
- 15 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Featuring the new Tensilica Vision Q7 DSP IP for Vision and AI

References4U

In this week’s Whiteboard Wednesdays video, Pulin Desai talks about the latest addition to the Vision DSP family, the Vision Q7 DSP. The Vision Q7 DSP offers up to 1.7X higher TOPS in the same area as Vision Q6 DSP. The Vision Q7 DSP provides 2X greater AI and floating-point performance compare to Tensilica Vision Q6 DSP. It is also optimized for simultaneous localization and mapping (SLAM) through instruction and architectural…
- 15 May 2019
Analog/Custom Design: Virtuosity: Did My Checks Pass or Did They Not Run?

AdityaMainkar

If you've ever tried to run the Checks/Asserts flow in Virtuoso ADE Assembler and Virtuoso ADE Explorer, you might have found it difficult to distinguish between “all checks passed” and “no checks were run”. In both the cases, the message “No violations” was displayed. Now, in IC6.1.8 ISR3 and ICADVM18.1 ISR3, you can differentiate when checks were not run or if they were ignored with syntax errors.
- 14 May 2019
Breakfast Bytes: After Meltdown and Spectre

Paul McLellan

At the recent Linley Spring Microprocessor Conference, the second day's keynote was by Jon Masters of Red Hat. He wears two hats (both of them red) since he is responsible both for their Arm product line and also their response to the Spectre and...
- 14 May 2019
Digital Design: LIBERATE 19.2 Base Release Now Available

LIBERATE Team

The LIBERATE 19.2 production release is now available for download at Cadence Downloads.

For information about supported platforms, compatibility with other Cadence tools, and details of key issues resolved in the LIBERATE 19.2 release, see the README.txt file.

At the time of publishing, the link above was functional. If you encounter any links that are now obsolete, visit https://downloads.cadence.com, click the LINUX…
- 13 May 2019
Breakfast Bytes: Bob Smith on ESD Alliance, ES Design West...with Wine

Paul McLellan

I talked to Bob Smith recently about what's coming up in the world of the ESD Alliance now that it is part of SEMI. One thing that Bob told me is that finally there are baby steps being taken outside of the US (Silicon Valley even) with a two-hou...
- 13 May 2019
Breakfast Bytes: Sunday Brunch Video for 12th May 2019

Paul McLellan

https://youtu.be/E61e34IbaRE Made at CDNLuve EMEA (camera Andrea Huse) Monday: Statistical Power...or Why You Shouldn't Be Allowed to Turn Right on Red Tuesday: JasperGold: the Next Generation Wednesday: How Do Out-of-Order Processors W...
- 12 May 2019
PCB、IC封装：设计与仿真分析: 通过人工神经网络探讨信号完整性的未来

Sigrity

想象一下，如果电脑或机器人可以完成所有枯燥乏味的工作，我们就能享受生活、做更多有意义的事。这些绝对是许多学术界、工业界研究人员的愿望。工程师的最终梦想是，按下一个“魔法按钮”，自动实现产品的设计、layout和优化，并满足性能参数和可制造性，这依然是科幻小说的情节，但现在各种实验设计（DOE）的运用使得技术已取得巨大的进步，特别是人工神经网络（ANN）。 space 正如我们所知，人工智能和神经网络的概念已经存在了几十年。直到近期，在2015年左右，相对“廉...
- 10 May 2019
Digital Design: HLS Optimizations You Can't Do By Hand

SeanDart

In my previous blog post, I talked about the Quality-of-Results (QoR) that are achievable using High-Level Synthesis tools like Stratus HLS and the fact that exploration of multiple RTLL architectures is often the feature that enables HLS users to beat hand-coded RTL flows in terms of QoR. That article raised the notion that "project schedule" is a critical factor when judging comparative QoR, and it often gets left out…
- 10 May 2019
Breakfast Bytes: 150th Anniversary of the Transcontinental Railroad

Paul McLellan

150 years ago, technology meant railroads, not semiconductors. I mean, precisely 150 years ago—today is the 150th anniversary of the completion of the transcontinental railroad from Oakland to Omaha, completed with a golden spike. I had a frien...
- 10 May 2019
System, PCB, & Package Design : Finally, A Certified and Correlated Reference Flow for Advanced Package Designs

Sigrity

As transistor device scaling gets closer and closer to physical limits, more and more companies have been looking beyond silicon and into multi-die approaches with advanced packaging to keep the innovation and speed performance trend going forward i...
- 9 May 2019
Analog/Custom Design: Virtuosity: The Top 3 Post-Layout Enhancements in Analog Design Environment

Arja H

Have you ever wanted to sweep DSPF files across corners, plot terminal current and voltage and ensure that the simulator name maps correctly to the schematic name in Virtuoso ADE Assembler and Virtuoso ADE Explorer? If so, IC6.1.8 ISR3/ICADVM12.8 ISR3 will be the release for you.
- 9 May 2019
Breakfast Bytes: Intel at Linley

Paul McLellan

At the recent Linley Spring Microprocessor Conference, there were two presentations by Intel about deep learning. The first was by Ian Steiner, the lead architect for Cascade Lake. The second was by Carey Kloss, the VP of Hardware for the AI products...
- 9 May 2019
Verification: Concurrent Actions in Specman: Part 2

teamspecman

In the previous blog: Concurrent Actions in Specman, we discussed the existing options: all of (which awaits completion of all branches) and first of (which terminates at the first completion of any branch). In 19.03 we added enhancement on top of these existing options, we made them more dynamic.

In all the examples in the previous blog, the number of branches was constant (all the examples used 2 branches). What if…
- 8 May 2019

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