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Earlier this year, we performed the annual high-level synthesis (HLS) industry survey to get an idea of the industry’s expectations of HLS. As in last year’s survey, approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on HLS usage and expectations.

As usual, I’ll walk through the questions one by one below, but first let…

For years chip designers have dealt with ECO’s when their source code was written in RTL. But the move to high-level synthesis (HLS) means that their source code is now one step further removed from the gate level netlist. This naturally leaves a question, “What if I need an ECO on my Stratus project?”

First and foremost, it’s important to understand that ECO’s are less common in the HLS flow. I’ll explain…

Veriest, a member of the Cadence Verification Alliance, is holding a series of Meetups in Serbia to serve the growing technology community. The December 12th event will feature a session on Specman Elite macros and how they help with reusability and maintainability.

Veriest is a long time Verification Alliance member, and recently co-authored a paper with Valens on DVCon on the same topic: "Learn How Valens uses…