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Digital Design: Are You Planning To Synthesize Your Design? Do You Want To Explore the Synthesis Flow in Genus Synthesis Solution?

Neha Joshi

A Logic Synthesis is a process of optimizing the design's area, timing, and power.

You might be a beginner in the synthesis world, but we can help you sail through it smoothly. It's time to introduce yourself to our tool for synthesis, Genus Synthesis Solution.

The ultimate goal of the Cadence^® Genus Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL…
- 9 May 2022
Breakfast Bytes: Linley: Western Digital's RISC-V Strategy

Paul McLellan

Western Digital acquired SanDisk in 2016. In 2017, Martin Fink, then the CTO of Western Digital, announced that it would convert all the cores used on its devices to RISC-V. This was one of the first solid commitments to RISC-V in a commercial s...
- 9 May 2022
PCB設計／ICパッケージ設計: BoardSurfers: IPC-2581の利用によるレイヤースタックアップデータの受け渡し

SPB Japan

設計意図やスタックアップ情報を設計の初期段階のうちに製造部門や製造委託先と共有しておけば、製品設計に影響を与え製品納入を遅らせてしまうような製造やアセンブリ関連の問題を回避することができます。しかし、製造データをやり取りするための標準的なコミュニケーション手段を持たない場合、レビューサイクルの中で情報が誤って解釈されたり、完全に失われたりする可能性があります。また、手作業で作成されたデータは統一性に欠け、必要なパラメータが不足している可能性もあります。もしも設計側と製造側の双方がIPC-2581...
- 8 May 2022
Breakfast Bytes: Sunday Brunch Video for 8th May 2022

Paul McLellan

https://youtu.be/xADMKcqKLNg Made on Communication Hill with Sheep (camera Carey) Monday: Gabrièle Saucier on the History of IP Tuesday: ESD Alliance CEO Outlook 2022 Wednesday: Always On at D&R Thursday: A History of Cadence in the C...
- 8 May 2022
Digital Design: Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to Conformal?

FormerMember

No matter how your name is spelt in different countries, and how they say it, once they get to know you, people identify you as the same person.

Ah! this is Chris, Cris, Kris, Kirshner, or Krishna. And I know this dude, even though he has transformed since I last saw him, and is 10 years older than what I remember.

Likewise, different tools have different ways of naming the same design object and the default rules rarely…
- 7 May 2022
PCB、IC封装：设计与仿真分析: 如何建立一个数据中心：全靠 SerDes和散热

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“How to Build a Data Center: It's All About the SerDes...and Thermal”。 space 我们可能不需要建立一个数据中心，但很可能会参与设计用于数据中心的芯片；或者在关注数据中心的 IP；或者担心先进节点设计工具的某些方面，其中大部分会发生在数据中心。因此，很有必要简单...
- 6 May 2022
Digital Design: Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI?

Neha Joshi

What comes to your mind when we say Genus Layout GUI (Graphical User Interface)? You picture the floorplan filled with instances and objects. Imagine you need to highlight the specific instance or timing path in GUI?

Do you think it’s tricky? Not at all!!

Genus Synthesis Solution GUI (Graphical User Interface) helps you view and highlight the instances and timing results to better explore/debug your design.

Now think…
- 6 May 2022
Breakfast Bytes: An Interview with Morris Chang

Paul McLellan

A couple of weeks ago, Morris Chang, the founder of TSMC and, for a long time (twice), its CEO, was interviewed at the Brookings Institution and the Center for Strategic and International Studies (CSIS), two think tanks in Washington DC. Th...
- 6 May 2022
System, PCB, & Package Design : ASCENT: Reasons to Move to 17.4-2019 HotFix SPB17.40.028 of Allegro Pulse

Auromala

HotFix SPB17.40.028 of 17.4-2019 of Allegro® Pulse is out and is available for download. This release includes various enhancements, new features, and product changes that address design challenges. Let’s look at some of the Alle...
- 6 May 2022
PCB、IC封装：设计与仿真分析: AWR：智能射频设计

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“AWR: Intelligent RF Design”。 space 今年AWR Design Environment® 推出的新版本V16具有跨平台的工作流程，支持基于 Virtuoso®（芯片）和 Allegro®（PCB/封装）平台的射频到毫米波设计，并与系统级分析解决方案 Clarity 3D Solve...
- 5 May 2022
Breakfast Bytes: A History of Cadence in the Cloud

Paul McLellan

Cadence Cloud started before there even was a cloud. We just didn't call it Cadence Cloud. Back in the early 2000s, when I was on my first tour of duty at Cadence, we created something that we called Virtual CAD, or VCAD for short. The idea was that ...
- 5 May 2022
Verification: Enflame Accelerates the DFT and DFD Verification using Palladium

Vinod Khera

DFT (Design for Testability) provides the much-needed support to the manufacturers to catch up with the increasing demand and pressure for mass production. It helps produce chips with flawless design and perfect quality for challenging applications. ...
- 5 May 2022
System, PCB, & Package Design : This Month in IDA

Sherry Hess

This month the In-Design Analysis (IDA) team kicked off its new blog program with an insightful look at "High-Tech Everything” from group director Sherry Hess and advice from our Celsius expert Melika Roshandell on "Finding and fixing thermal issues early in the PCB design flow."
- 4 May 2022
PCB、IC封装：设计与仿真分析: OMNIS – 如何在汽车领域应对当今和未来的多物理场仿真挑战？

SDA China

本文作者：Yannick Baux, Cadence产品研发总监 space 汽车行业一直使用 CFD 工具来设计和优化车辆的各个方面，从外部空气动力学到降噪，再到热管理、内部燃烧等等。大多数情况下，在设计过程中，所有上述内容被结合在一起，称为虚拟原型，以便将车辆作为一个系统进行优化。然而，各种应用背后的物理原理往往大不相同，这就意味着需要为每个特定的应用采用专门的技术。因此，设计师、科学家或工程师经常使用大量不同的 CAE 代码和软件工具，这些工具都有不同的界面（GUI）、数据设置、...
- 4 May 2022
Academic Network: Virtuoso Education Kit Available Now

Anton Klotz

The Cadence Education Kit initiative runs at full steam! After the release of the VLSI Fundamental: A Practical Approach Education Kit and the Tensilica Education Kit, there is a new kit knocking on the door of all microelectronics educators: the Fun...
- 4 May 2022
Breakfast Bytes: Always On at D&R

Paul McLellan

At the recent D&R IP-SoC Day 2022, Amol Borkar presented Designing the Next Ultra-Low Power Always-On Solution. Amol is a product marketing director for the Cadence Tensilica product line. He started with some statistics about Tensilica. Tensilic...
- 4 May 2022
PCB、IC封装：设计与仿真分析: 如何在PCB设计中进行DDR布线？

TeamAllegro

DDR布线技术的重要性在如今的印刷电路板设计中，双数据速率（DDR）存储器非常普遍。许多设计都会用到DDR存储器配置的不同版本，这需要在布局中使用特定的布线模式。DDR的名称来源于其能够在每个时钟周期内发送和接收两次信号，是原先的单数据速率（SDR）存储器速率的两倍。由于速率增加了一倍，必须在布设DDR存储器的走线时保持更严格的参数，以满足性能规范。存储器电路设计的关键在于满足其时序规范。每个信号都有时间要求，以便于对应的时钟信号在上升沿和下降沿对其采样。由于数据速率在DDR存储器的每次新迭...
- 3 May 2022
Breakfast Bytes: ESD Alliance CEO Outlook 2022

Paul McLellan

Last week was the ESD Alliance CEO Outlook. It was hosted by Keysight (fka Agilent fka Hewlett-Packard) who, in addition to providing an auditorium, provided us all with excellent food and drink. ESD Alliance Annual Members Meeting Actually, the meet...
- 3 May 2022
Verification: How AMBA CHI Specification Has Evolved - CHI-E (r)evolutionary?

MinL

We covered CHI specification revisions A to D in my previous article, what about Issue E?

Issue E was by far the biggest update yet with a slew of new transactions, optimization features to interface behavior and architecture, and spec clarifications and corrections. It spanned two years and two sub releases (E.a and E.b).

2020 (CHI-E.a) Issue E.a – update

Issue E.a added new transaction types such as Write*Zero…
- 2 May 2022
PCB、IC封装：设计与仿真分析: 详解时域瞬态分析技术

Sigrity

本文要点：所有的物理系统在运行动态中都会表现出一些瞬态行为，电子产品也是如此瞬态分析技术可以帮助了解不同电气状态之间的转换当检查测量数据或软件仿真数据时，一些基本的瞬态分析技术可用于了解电气状态之间的转换时域瞬态分析技术在时域中运用，全面展现了不同状态之间的信号转换过程当打开或关闭 LED 时，随着光线变亮或变暗有一个缓慢的过渡。这种类型的瞬态行为非常简单，但这是一个电子系统改变状态时的基本反应。使用瞬态分析可以充分理解时域中的信号转换，以及它们与重要系统参数的关系。初次接触软...
- 2 May 2022
The India Circuit: SemiconIndia 2022 Conference: A First-of-Its-Kind

Madhavi Rao

The Ministry of Electronics and Information Technology (MeitY) organized a unique conference this past weekend called SemiconIndia 2022. Inaugurated by Prime Minister Modi, other dignitaries from the government of India included Minister of Electroni...
- 2 May 2022
Breakfast Bytes: Gabrièle Saucier on the History of IP

Paul McLellan

Recently, it was D&R's IP-SoC Silicon Valley 2022. The opening keynote was given by Gabrièle Saucier, the CEO of D&R. It was also the 25th anniversary of D&R. But I met Gabrièle years before that. In December 1986, I rel...
- 2 May 2022
Computational Fluid Dynamics: Fidelity CFD Overset Meshes to Simulate Rotor Hub Vortex Shedding in Helicopters

Veena Parthan

Vortex shedding in a helicopter rotor hub can be analyzed and captured precisely using Fidelity CFD overset meshing.
- 1 May 2022
Breakfast Bytes: Sunday Brunch Video for 1st May 2022

Paul McLellan

https://youtu.be/TERyp8U7PCY Made at Parker Ranch, Saratoga (camera Carey) Monday: DesignCon: Google on AI for Non-AI People Tuesday: Asianometry Wednesday: Linley: AI Moving to the Edge Thursday: Syntiant Wins MLPerf TinyML Benchmark (with...
- 1 May 2022
PCB、IC封装：设计与仿真分析: NUMECA、CFD与美洲杯帆船赛

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章"NUMECA, Computational Fluid Dynamics...and the America's Cup"。 space 什么是计算流体力学（CFD）？美洲杯帆船赛（America's Cup）与其有何关系？今年美洲杯帆船赛的卫冕冠军是新西兰酋长队，他们制胜的秘密武器是使用了NUMECA FINE /Mari...
- 29 Apr 2022

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