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Computational Fluid Dynamics: This Week in CFD

Paul McLellan

It’s a good Friday for the latest roundup of CFD flotsam and jetsam from the ocean that is the internet. [Making this the Great CFD Garbage Gyre?] We use the marine theme because, for unexplained reasons, there are a lot of marine applications ...
- 2 Apr 2021
System, PCB, & Package Design : ASCENT: Ready, Steady, Design ... Even With Existing Libraries

Rachna2018

After a quick overview of Allegro® System Capture, let’s start at the very beginning of the design process. Where are the parts? What parts can you use when creating an Allegro System Capture logical design? Parts, as you know, are the basi...
- 1 Apr 2021
Breakfast Bytes: Offtopic: Podcasts

Paul McLellan

Tomorrow is another Cadence global holiday. None of us will be working and Breakfast Bytes will not appear. I rather like these special Cadence holidays, compared to true public holidays, since most people are working. If you go to a park, the p...
- 1 Apr 2021
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: EMX Planar 3D Solverで受動素子と能動素子を持つRFブロックをシミュレートするには？

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 1 Apr 2021
カスタムIC／ミックスシグナル: Start Your Engines: SimVision Mixed-Signal Debug Optionを使ってル・マンで優勝する

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 Bonjou...
- 1 Apr 2021
Computational Fluid Dynamics: Resolving Boundary Layers with Unstructured Quad and Hex Meshing: On-Demand Webinar

Paul McLellan

All things being equal, CFD practitioners prefer to use hexahedral mesh cells in the boundary layer for the improved robustness and accuracy they bring to the flow solver. Traditionally, a hex grid would be created using a structured grid technique (...
- 31 Mar 2021
Breakfast Bytes: The First Commercial Computer Shipped 70 Years Ago Today

Paul McLellan

Today is the 70th anniversary of a very significant event in all our lives, even if few of us were alive back then. Exactly 70 years ago, March 31, 1951, the first commercial computer shipped. You might assume that the first computer was shipped...
- 31 Mar 2021
System, PCB, & Package Design : (P)SpiceItUp: Generating ISO 7637-2 Standard Pulse 2a in PSpice A/D

Shailly

Many times, you would have required to create a standard pulse waveform that can be used for testing devices as per the industry standard. One good example is to simulate the ISO 7637-2 transient at the schematic design stage. This practice ensures t...
- 30 Mar 2021
Digital Design: Library Characterization Tidbits: Define Measurements to Suit Your Characterization Requirements

Jommy

Do you have a requirement to specify measurements that are not default while performing memory characterization? Liberate MX has a solution for you.
- 30 Mar 2021
定制IC芯片设计 : Virtuoso Meets Maxwell：为什么没有提到引线键合IC？

Steve PDK Lee

当今的许多模拟，RF和混合信号设计都要求在同一模组内部集成多个不同工艺的IC，以实现所需的性能目标。设计师使用异构器件集成方法能够获得单片IC (SoC) 设计上不容易达到的结果。与此同时对设计师而言，异构集成也是全新的挑战。
- 29 Mar 2021
Breakfast Bytes: Intel IDM 2.0

Paul McLellan

You've probably read in the press that Intel's new CEO, Pat Gelsinger, laid out his vision for Intel's future last week. You probably also know that, as he put it, "I've spent four decades in this industry, three of them here at ...
- 29 Mar 2021
Analog/Custom Design: Spectre Tech Tips: Detecting Leakage Path Current Hotspots

Stefan Wuensche

In circuit design, wrong connectivity may cause undesired leakage paths that may result in current hotspots. These current hotspots can be quickly identified with Spectre’s dynamic design checks. This blog describes how to use the Spectre design checks to identify the root cause of leakage path current hotspots.
- 28 Mar 2021
Digital Design: Pegasus: Get Your Wings: Virtuoso/Pegasus In-Design Signoff

Sarita Sharma

The beauty of Pegasus is that it doesn’t only work excellently in standalone mode but also seamlessly integrates with other tools such as the industry-standard Virtuoso custom/analog platform and enables users to complete advanced-node DRC in h...
- 26 Mar 2021
Breakfast Bytes: Stopping Online Fraud

Paul McLellan

I attended a webcast on Anti-Fraud organized by the RSA Conference in the leadup to the conference itself. It will be virtual, of course, and it will be held from May 17 to 20. If any aspect of your job involves security, or you are just interested, ...
- 26 Mar 2021
Analog/Custom Design: Virtuoso Video Diary: Tabular Graph in Virtuoso Visualization and Analysis XL

YaswanthSai D

Do you know you can now use Tabular Graph feature in Virtuoso Visualization and Analysis XL to analyze waveform data. Click here to know more.
- 25 Mar 2021
Academic Network: Cadence on YouTube

Anton Klotz

One of the most popular platforms of the whole Internet is undeniably YouTube; this is a place where every user can upload and watch videos about all topics that mankind has ever defined as interesting or worthwhile show...
- 25 Mar 2021
Breakfast Bytes: Best of CadenceLIVE 2020: Hyperscale Data Centers

Paul McLellan

There is something in philosophy known as the Sorites paradox. If you have a heap of sand, and you remove a grain, is it still a heap? Well, sure. So, remove another grain. It's still a heap. But if you keep removing sand, do...
- 25 Mar 2021
Life at Cadence: Women’s History Month Reflections with Alessandra Costa

Mary Kasik

Women’s History Month looks at the achievements women have made over the years. It is a time to honor the women in our lives who have made a difference and encourage the continued advancement of gender equality. At Cadence, we want to recogniz...
- 24 Mar 2021
RF /マイクロ波設計: [4月9日開催] CadenceTECHTALK 5G/6Gのシステム解析を加速する AWRと3D Glass Solutions

RF Design Japan

　ケイデンスでは、これまで定期的にオンラインセミナーを開催し、高周波設計向けソリューションを紹介して参りました。今回は、5Gや今後の6Gのような無線通信に向けた取り組みとして独自の加工技術により注目されている3D Glass Solutions(３DGS)社の技術を紹介させて頂くWebinarを企画いたしました。３DGS社が用意する設計キット(PDK)は弊社のCadence AWR設計環境向けに用意されており、お客様の設計を効率化する弊社のユニークで強力な機能がふんだんに盛り込まれています。 ...
- 24 Mar 2021
Breakfast Bytes: National Security Commission on Artificial Intelligence

Paul McLellan

The (U.S.) National Security Commission on Artificial Intelligence recently published its final report. The report is 756 pages long, so I am not going to claim that I've read it all. I read the introduction and some of the conclusion, and the ch...
- 24 Mar 2021
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: EMX — 業界をリードするRFIC用電磁界ソルバー

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 23 Mar 2021
Verification: TileLink: Chip-Scale Cache-Coherent Interconnect Protocol

RashmiMathanKumar

RISC-V, an open specification of an Instruction Set Architecture (ISA), which was designed to be scalable for a wide variety of applications has been enjoying wide-spread adoption in the industry.

TileLink is a free and open standard chip-scale interconnect protocol designed for RISC-V processors and beyond (could be used with other ISAs as well). It’s a fast scalable SoC communication protocol designed to connect multiprocessors…
- 23 Mar 2021
System, PCB, & Package Design : IC Packagers: How to Quickly Push Design Connectivity across a Design

avijeet

The task of IC/package co-design causes multiple challenges during the design cycle and one of them is to update the netlist of co-design die or BGA in the middle of the design cycle. The current process of updating connectivity provides no flexibili...
- 23 Mar 2021
Analog/Custom Design: Virtuoso ICADVM20.1 ISR17 and IC6.1.8 ISR17 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR17 and IC6.1.8 ISR17 production releases are now available for download.
- 23 Mar 2021
Spotlight Taiwan: Sigrity X 2021 盛裝登場!

candyyu

原文出處: Announcing Sigrity X作者: Paul McLellan 在EDA領域中運用了許多不同的運算軟體。然而EDA產業所面臨的挑戰在於，設計團隊總需要採目前處理器來設計及創建下一代的SoC。然而，在1990年代和2000年代，微處理器公司（主要是英特爾，但也包括Sun、HP、Digital等）將處理器的性能每年提高約50％來解決這個問題，部分是因為摩爾定律 - 在沒有產生電源問題的同時，提高矽晶片的性能；還有部分來自於處理器的架構的提升，以更聰明的方法來執行...
- 23 Mar 2021

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