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Verification: Transport Layer – The Backbone of a USB4 Router

Neelabh

It won’t be incorrect to say that the transport layer of a USB4 router is the backbone of it. It is a layer that holds all the various other layers together. It provides the very essential services like paths and routing for tunneled traffic, various types of flow control, link management, which are some of the core features that make a USB4 router work the way it should.

A path is like a virtual wire, which is…
- 11 Mar 2021
Breakfast Bytes: Best of CadenceLIVE 2020: The Keynotes

Paul McLellan

The first CadenceLIVE 2021 will be CadenceLIVE Americas on June 8-9. It will be a digital experience. The call for presentations is already open—submit an abstract on this page before it closes on March 24. Also, registration has just opened. I...
- 11 Mar 2021
Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster Training Bytes - Part 6

Parula

In this blog. we would like to let you know the information on how to achieve complete full-chip DRC signoff on advanced-node designs and efficiently run multiple DRC signoff iterations.
- 10 Mar 2021
System, PCB, & Package Design : Designing the Allegro System Capture Way

Rachna2018

A design starts in the mind of an architect, gets drawn on whiteboards as basic block diagrams that describe a system. Next, designers see what can be reused from older designs, schematics get drawn, parts are identified, from in-house libraries or from online vendors. If the available parts don’t match their requirement, librarians are asked to create or modify parts. Then checks and rules are run to ensure design integrity…
- 10 Mar 2021
Breakfast Bytes: Paul Cunningham's DVCon Keynote: Verification Throughput = Engines × Logistics

Paul McLellan

At DVCon 2021, the keynote was presented by Cadence's Paul Cunningham who is basically Cadence's Mr. Verification (officially he is Corporate VP and General Manager of System & Verification Group). He titled his presentation Computation...
- 10 Mar 2021
Digital Design: Voltus Voice: Demystifying ESD — Four Simple Steps to Run ESD Analysis Full-Chip Flow

Vijetha

This blog post outlines four simple steps for analysis of your electrostatic discharge (ESD) protection circuitry using the Voltus ESD Analysis solution.
- 9 Mar 2021
Academic Network: One-Stop Pages on support.cadence.com

Anton Klotz

This is intended for active users of Cadence Learning and Support. If you’re not a user yet, it’s easy to start! All academic users of Cadence software have the opportunity to access the support page. Students, please contact your profess...
- 9 Mar 2021
Breakfast Bytes: Let’s Talk About Chiplets, Baby

Paul McLellan

At CadenceLIVE Americas 2020, one of the most viewed videos was by Samsung Foundry's Kevin Yee and Cadence's Tom Wong. Despite the title of this blog post, the title of their presentation was a bit longer: Let’s Talk About Chips (Chiplets), Bab...
- 9 Mar 2021
Analog/Custom Design: Virtuoso Meets Maxwell: EMX—Industry-Leading EM Solver for RFICs

scottd

Hi all, this is my first blog for the Virtuoso Meets Maxwell series. It builds on the Virtuoso Meets Maxwell 2021 introduction blog. Today I get to discuss one of my favorite topics, electromagnetic (EM) analysis of RFICs using Cadence EMX Planar 3D Solver.
- 8 Mar 2021
カスタムIC／ミックスシグナル: Start Your Engines: ミックスシグナル・テストベンチ用自動コンフィグレーション生成

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 Bonjou...
- 8 Mar 2021
Breakfast Bytes: Your Best Buys Are Always at Fry's

Paul McLellan

A Silicon Valley institution has shut down. Fry's electronics says on their website: After nearly 36 years in business as the one-stop-shop and online resource for high-tech professionals across nine states and 31 stores, Fry’s Electronics, In...
- 8 Mar 2021
Breakfast Bytes: Sunday Brunch Video for 7th March 2021

Paul McLellan

https://youtu.be/71UiX5Ce9cE Made autonomously driving in San Francisco Monday: Update: Hogan, Mars, Australia, Solarwinds Tuesday: Cruising Through San Francisco with No Driver Wednesday: Computational Software for Cyber-Physical System Design Thurs...
- 7 Mar 2021
RF /マイクロ波設計: 野外でのIoT向けマルチバンドアンテナ—新しいホワイトペーパー(英語)

RF Design Japan

　大規模なマシンタイプの通信（mMTC）と、拡張されたモバイルブロードバンド（eMBB）および超高信頼性の低遅延通信（URLLC）は、3GPPによって定義された5Gイニシアチブの3つの柱を表しています。 5G mMTCの1つの目標は、膨大な数の固定およびモバイルIoTデバイスにスケーラブルな接続を提供することです。デバイス自体は、クラウドへのワイヤレス接続を通じてさまざまなセンシングおよび動作機能をサポートします。　これらのリモートデバイスは、サービスを提供せずに何年に...
- 6 Mar 2021
RF Engineering: Multi-Band Antennas for IoT on the Go — New White Paper

StandingWaves

Massive machine type communications (mMTC) along with enhanced Mobile Broadband (eMBB) and Ultra Reliable Low Latency Communications (URLLC) represent the three pillars of the 5G initiative defined by the 3 GPP. One goal of 5G mMTC is to provid...
- 5 Mar 2021
System, PCB, & Package Design : Boardsurfers: An Introduction to Allegro DesignTrue DFM Rule Aggregator

Sarbjit

Design companies often work with multiple PCB fabricators and each fabricator may have a different set of DFM rules. It is a customary practice followed by design companies to create a common denominator rule set that can be applied to all fabricator...
- 5 Mar 2021
Breakfast Bytes: Bootstraps

Paul McLellan

How does an operating system get started? Obviously, if the operating system was already running, you could get it to load the operating system from the storage media. But the operating system is not running, that is the problem that you ar...
- 5 Mar 2021
Digital Design: Library Characterization Tidbits: Importance of Noise Analysis and the Role that Liberate Plays

Moinak Gorai

The hustle bustle of the cities is only an example of the external noise, which we are aware of through the obvious observations of our sensory organs. However, in terms of electronics, a noise maybe defined as any kind of unwanted signal that interferes with the real signal in a timing path in a cell or circuit. Modeling of accurate noise characteristics at the cell level and being aware of the possible failures early…
- 4 Mar 2021
RF /マイクロ波設計: Discover System Analysis Monthly Newsletter(翻訳版)

RF Design Japan

日本語翻訳版をお届けします。ぜひ最新の製品に関する最新の情報をご確認ください。システム解析のニュースレターのご購読はこちらからお申し込みください。創造するために革新する| システム解析と分析システムモデル、解析、分析は複雑すぎてすぐに理解できないことがよくありますが、このコンテンツの蓄積が、コミュニティとインスピレーションを与えて、課題を再考し、画期的なソリューションを作成できることを願っています。送電線の電圧変動率：依存関係とパラメータ送電線の電圧変動率に対する線パラメ...
- 4 Mar 2021
Breakfast Bytes: Lip-Bu Tan Honored with SVBJ C-Suite Award

Paul McLellan

For the last few years, the Silicon Valley Business Journal has honored occupants of the C-suites in Silicon Valley companies: CEOs, CTOs, corporate counsels, CIOs, CFOs, and so on. As the journal explains on its website: In the fourth annual C...
- 4 Mar 2021
Breakfast Bytes: Computational Software for Cyber-Physical System Design

Paul McLellan

The recent 34th International Conference on VLSI Design, also known as VLSID, was a virtual event, of course. But it is India-based and the conference ran on India time. The theme for this year was From the Transistor to Cyber-Physical...
- 3 Mar 2021
Breakfast Bytes: Cruising Through San Francisco with No Driver

Paul McLellan

You probably have heard that Waymo has completely driverless (no safety driver) taxis serving Phoenix. 600 of them. But you can't go and buy one. Why is that? Paul Graham, the founder of the incubator Y Combinator is celebrated for many reasons,...
- 2 Mar 2021
Breakfast Bytes: Update: Hogan, Mars, Australia, Solarwinds

Paul McLellan

I don't normally do these updates this frequently, and never before have I produced an update on a post from just a week ago. Jim Hogan RIP One of my mentors passed over the weekend from a heart attack. Jim was one of the earliest employees of SDA, ...
- 1 Mar 2021
RF /マイクロ波設計: お客様発表『 Fast MMIC Design with Distributed EM Analysis』のご案内

RF Design Japan

概要回路および電磁界（EM）解析を単一のコンピュータ上の複数のプロセッサ間または外部のリモートコンピューティングファーム全体に分散する機能により、リソースを大量に消費するMMIC、RFIC、およびファブリック間の設計問題の全体的な解析時間を大幅に短縮できます。並列計算を活用することで、設計チームはEMレベルの精度でオンチップ部品の値を容易に最適化し、数千とは言わないまでも数百回の最適化の反復を通じて設計オプションを完全に調査し、大規模システム（チップ、パッケージ、ボードアセンブリ）の性能を検...
- 28 Feb 2021
PCB設計／ICパッケージ設計: BoardSurfers: 17.4-2019に追加されたダイナミックシェイプの 'Fast' モードは本当に早い！

SPB Japan

私は Allegro® PCB design のソフトウェアのテストを20年間担当していますが、あごがはずれるほどびっくりする機能をテストすることが時々あります。今年、新しいFast シェイプモードについて私はそんな驚きを体験し、これは皆さんに伝えなくては、と感じました。なぜなら、ポジティブシェイプを扱う作業を大きく変える、パフォーマンスとシェイプ表示クォリティの両面において画期的な機能だからです。エッチシェイプの数が増え、あるいはポジティブシェイプの増加に伴ってデータベースが肥大化す...
- 28 Feb 2021
Verification: Webinar: Extend the Language Using Specman e Macros!

teamspecman

Using Cadence^® Specman^® Elite macros lets you extend the e language ─ i.e. invent your own syntax.

Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and some are very advanced utilities implementing sophisticated methodologies. With macros, you can replace long complex user code with much shorter and simpler code. And, as we know – the shorter the code is, the less…
- 28 Feb 2021

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