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Breakfast Bytes: Photonics: How Do You Attach Fiber to the Chip?

Paul McLellan

Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution to High-Performance Computing. You can read my earlier posts: Photonic Integration—From Switching to Computing How to Design Photonics If You Don't Have ...
- 9 Dec 2020
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: システム解析と実装を可能にするためのライブラリ構築

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 8 Dec 2020
System, PCB, & Package Design : IC Packagers: Leaving Yourself Reminders in Your Designs

Tyler

Are you like me? Do you forget things and have a running to-do list for your designs? Would you like to leave instructions and comments for your colleagues to remind them of actions needing doing? There are many places to record this type of informat...
- 8 Dec 2020
Breakfast Bytes: How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs

Paul McLellan

Last week was the virtual event CadenceCONNECT: Photonics Contribution to High-Performance Computing. The opening keynote was by Odile Liboiron-Ladouceur who leads a team working on photonics at McGill University in Montréa...
- 8 Dec 2020
RF /マイクロ波設計: RF Design Japan: RF/マイクロ波設計のブログを開設します。

RF Design Japan

新しいRF / Microwave Designブログシリーズがオンラインのケイデンスコミュニティに参加し、日本の読者にケイデンスAWR RF製品のショーケースとしてサービスを提供しています。このブログは、RF /マイクロ波MMIC、PCB、およびモジュールの設計者が関心を持っている問題に焦点を当てており、高周波電子機器、リリース情報、技術記事の日本語翻訳に関連する今後のローカルおよびオンラインイベントを紹介しています。新しいブログカテゴリには、Communityページの左側にある灰色のパネ...
- 8 Dec 2020
カスタムIC／ミックスシグナル: Virtuosity: Conserve Power— Virtuoso Power Managerの前置き

Custom IC Japan

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso Power Managerの機能と可能性をご紹介します。今後のこのミニ・シリーズの投稿にご注目ください。電力消費は、常に電子設計における最優先事項です。消費は、回路で使用される電力だけではなく過熱を防ぐための回路のモニタリングにも関係します。電子製品のバッテリー寿命が、成功への決定的要因になり得ます。設計者は、デザインの性能に影...
- 7 Dec 2020
Life at Cadence: When One Door Closes...Opening New Doors with Cadence Retool-to-Work

BonnieW

I love the second half of this famous quote by Alexander Graham Bell “When one door closes another door opens; but we often look so long and so regretfully upon the closed door that we do not see the one which has opened for us.” With the...
- 7 Dec 2020
Verification: Xcelium Provides 3X Performance Increase for StreamDSP's FPGA-Based Defense IP

Ankur J

The FPGA market is rapidly growing in the traditional Aero-Defense sector as well as in the emerging sectors like Automotive and IoT. FPGA design is considered relatively simple compared to the complexities posed by an SoC design, but FPGA verification is not that simple. Traditionally, companies have been using FPGA vendor tools, methodologies, and flows for verification, but this is proving to be insufficient due to…
- 7 Dec 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Defining Standard Library Components

Tyler

The Allegro Package Designer product line offers everything needed to take an IC package from idea to manufactured part, and this is where the journey takes us today. It is available from your Virtuoso environment as Virtuoso MultiTech Framework.
- 7 Dec 2020
Digital Design: Pegasus: Get your Wings

Sarita Sharma

Pegasus: Get your Wings is a blog series to showcase the capabilities of Pegasus and to familiarize you with its notable features.
- 7 Dec 2020
Breakfast Bytes: CadenceCONNECT: Mission Critical - Tom Beckley's Keynote

Paul McLellan

In October, we held the CadenceCONNECT: Mission Critical event, focused on aerospace and defense (A&D). Tom Beckley gave the opening keynote. By background, many of the senior people in A&D historically knew little about electronics, nev...
- 7 Dec 2020
Breakfast Bytes: Sunday Brunch Video for 6th December 2020

Paul McLellan

https://youtu.be/r7utPfsdcKk Made in front of my living room fire Monday: What Is a Capability? CAP, CHERI, and Morello Tuesday: Cadence and Standards...and a New Codec for Your Phone Wednesday: Photonic Integration — From Switching to Computin...
- 6 Dec 2020
Life at Cadence: Enabling and Empowering OEMs to Design Chips

Corporate

Introduction Today, many original equipment manufacturers (OEMs), especially new-generation OEMs, are not shying away from taking ownership of their system-on-chip (SoC) designs and thereby sharing the IP rights with the chip makers. Traditional OEMs...
- 5 Dec 2020
Breakfast Bytes: Innovus for Digital 3D-IC Designs

Paul McLellan

A few weeks ago, there was a webinar about designing 3D-ICs with Innovus Implementation. Although it was not the topic of the webinar, I should point out that if your die is more custom/analog, then you can also design 3D-ICs in the Virtuoso env...
- 4 Dec 2020
カスタムIC／ミックスシグナル: Spectre Tech Tips: EMIR解析におけるSpectre Xの価値

Custom IC Japan

EMIR解析は回路シミュレーションの中でも難易度の高い分野の一つです。それは、後に実行されるIRドロップおよびEM電流解析のために、電力および／または信号ネットの寄生を保存する必要があります。同時に、EMIR解析では、ファウンドリで定義された電流制限に対してEM電流をチェックするために、SPICEのような精度が必要となります。Cadenceのトランジスタ・レベルのEMIR解析ツールであるVoltus-Fi XLは、Spectre EMIRソリューションを使用して、回路の動作をシミュレートし、IR...
- 3 Dec 2020
Analog/Custom Design: Virtuosity: Conserve Power—Verifying a Design Using Conformal Low Power

bsachin

If you have been following the Conserve Power blog series, you will probably have an idea of what next I am going to talk about. Yes, we have now reached the finale, the last and the most intriguing piece in the entire story. It is the formal verification and sign-off of the IP to make it ready to be integrated into an SoC.
- 3 Dec 2020
Analog/Custom Design: Virtuoso Video Diary: Why Split Symbols?

Parula

A blog that tells you about why splitting up blocks has now become a useful feature in more complex designs and advanced technology.
- 3 Dec 2020
Breakfast Bytes: Google's DeepMind's AlphaFold Solves Protein Folding

Paul McLellan

Solving protein folding has been a challenge for at least 50 years. You probably know that proteins are made up of amino acids, of which there are just 20. They are linked into long chains. How proteins behave depends on how they fold up. For ex...
- 3 Dec 2020
System, PCB, & Package Design : BoardSurfers: How to Install Allegro ECAD-MCAD Library Creator Server?

Sanjiv Bhatia

In addition to reducing package creation time by 60-80%, Cadence Allegro ECAD-MCAD Library Creator has the Library Creator repository, which provides thousands of ready-to-use packages and templates. The repository allows centralized configuration-controlled storage...
- 2 Dec 2020
Digital Design: Innovus Design Metrics: Visualize This!

VNelson

To arrive at your targeted and optimized PPA, you will need to execute several Innovus runs with a variety of design parameters, commands, and options.

You will then need to analyze the data which could mean wading through several log files and timing reports, a time-consuming task at best.

To make it easier to visualize the data by generating an easy-to-read dashboard, Innovus now has integrated metrics commands. These…
- 2 Dec 2020
Analog/Custom Design: Virtuosity: Our Design Thinking Approach to Enhance User Interfaces across Cadence Products

KomalJohar

Read our story about how teams across Cadence, diligently work towards enhancing your experience by continuously improving the quality of user interfaces from a usability aspect.
- 2 Dec 2020
Breakfast Bytes: Photonic Integration — From Switching to Computing

Paul McLellan

Last Tuesday was the first day of the virtual event CadenceCONNECT: Photonics Contribution to High-Performance Computing. Note that the subtext of this is actually using silicon photonics for performing high-performance computing, not just providing ...
- 2 Dec 2020
System, PCB, & Package Design : IC Packagers: Adding Multiple Component Instances without a Schematic

Tyler

More package designers these days, with the increasing component counts and more complicated electrical constraints, are shifting to using a front-end schematic capture tool. As with IC and PCB design, this allows for verification between the logical...
- 1 Dec 2020
Breakfast Bytes: Cadence and Standards...and a New Codec for Your Phone

Paul McLellan

A lot of EDA and IP is increasingly based around standards. As a result, Cadence is actively participating in and contributing to standards bodies such as IEEE, JEDEC, Accellera, and Si2 to name a few. Here are the most recent standards that we have ...
- 1 Dec 2020
PCB解析／ICパッケージ解析: Clarity、Celsius、およびSigrityツールの2019 HF4リリース(2020年11月) - 新機能ハイライト

SPB Japan

Clarity, Celsius, Sigrityツールの2019 HF4プロダクト・リリースがCadence Downloadsサイトからダウンロード可能となりました。2019 HF4リリースにおけるCCRの改修項目は、インストール階層に含まれているREADME.txtをご参照ください。 SIGRITY2019 HF4 以下では、Clarity, Celsius, Sigrityツール - 2019 HF4プロダクト・リリースの主なアップデートをいくつか紹介します。これらの機能や他のすべて...
- 30 Nov 2020

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