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定制IC芯片设计 : Virtuoso Meets Maxwell: Clarity 与有限元方法结合

Amir Asif

本文将介绍Clarity 的一些功能，当你需要使用基于FEM的电磁解算器用于 Virtuoso RF 解决方案时，Clarity 将会是您的最佳选择！
- 17 Dec 2020
Digital Design: Library Characterization Tidbits: Bidding Adieu to 2020

Jommy

This year all our “regular” routines were shaken up by COVID-19, which brought along many challenges for people all over the world.
- 17 Dec 2020
カスタムIC／ミックスシグナル: Virtuosity: Voltus-Fi-XL FAQ — よくある質問とその回答

Custom IC Japan

読者のみなさん、こんにちは！ Voltus-Fiに関する蒸留された知識をお探しなら、正しいページにお立ち寄りいただきました！何年にもわたって好奇心を持ち続け、さまざまなプラットフォームでのVoltus-Fiについて、単純なものから複雑なものまで、多くの質問をエキスパートに尋ねてきました。そしてエキスパートはそれらの質問に答えることで、迅速かつ効率的にユーザを助けてきました。そこで、私たちは独自のQ&Aバンクを開発し、必要なときにすぐに参照できる形式で保存することを考え、FAQドキュメン...
- 16 Dec 2020
Analog/Custom Design: Virtuosity: Moving Along the Least-Resistive Path in Voltus-Fi

Pallabi R

Do you want to know how discovering the path of least resistance for the devices of your design much ahead of your power planning can make your life easier? Then go ahead and read the blog.
- 16 Dec 2020
Life at Cadence: Chiplets and Heterogeneous Packaging Are Changing System Design and Analysis

Corporate

In the domain of electronic product design, solely relying on process shrink as the primary driver of product innovation and improved system performance is no longer a viable approach. The cost and complexity associated with advanced nodes has everyo...
- 16 Dec 2020
Breakfast Bytes: RISC-V: The Next Ten Years

Paul McLellan

The annual RISC-V Summit (virtual, of course) was in early December. You can read my first report in my post The 2020 RISC-V Summit. The second day started with a keynote by Krste Asanovic, the lead of the team that defined the RISC-V ISA. Krste...
- 16 Dec 2020
Analog/Custom Design: Spectre Tech Tips: Increasing Performance and Capacity Using Spectre X Distributed Simulation

FredIvar

The Spectre X distributed simulation is an extension to the multithreaded simulation where cores from different machines are used. The Spectre X distributed simulation provides access to more cores, thus increasing the performance and capacity and providing more value for large designs.
- 15 Dec 2020
RF Engineering: μWaveRiders: Cadence AWR EM Simulators Solve Complex RF/Microwave Structures for Design Success

TeamAWR

RF designers increasingly rely on electromagnetic (EM) simulations to characterize board designs before the first component is placed, and continue to use EM analysis right through manufacturing handoff. New capabilities in automation and EM analysis are critical as board designs become denser and new manufacturing processes allow you to squeeze more performance out of PCB designs.
- 15 Dec 2020
Digital Design: Wondering What to Do During the Winter Staycation? How about Learning Something New?

VNelson

We just recently released a training course that we are excited to tell you about.

The course is RTL-to-GDSII Flow.

This course is unique in that it takes a tiny design through a wide variety of Cadence tools so that you can gain some exposure to tools that you may not be familiar with.

You learn how to implement a design from RTL-to-GDSII using Cadence tools. You will start by learning how to code a design in VHDL or…
- 15 Dec 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: Running RAVEL Rules from Command Line

Niharika1

In one of the previous posts, we learnt about How to Run a RAVEL Rule from the GUI. The RAVEL rules that you write can be run from command line or Graphical User Interface (GUI) of Allegro® PCB Editor. You can also run these rules from Allegro&re...
- 15 Dec 2020
Digital Design: SSV 20.2 Base Release Now Available

SSV Release Team

The SSV 20.2 production release is now available for download at Cadence Downloads. For information about supported platforms, compatibility with other Cadence tools, and details of key issues resolved in the SSV 20.2 release, see ...
- 15 Dec 2020
System, PCB, & Package Design : IC Packagers: Comparing Design Versions to Find Physical Changes

Tyler

ECOs. Without them, the lives of designers would be so much easier! Imagine a world where the original requirements you were given never changed throughout the design. Unfortunately, such a world, as we know, does not exist. How, then, can you track ...
- 15 Dec 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Layered Electromagnetic Modeling For Sufficient Accuracy

Claudia Roesch

Fast growing markets like 5G, automotive, and IoT are driving the development of advanced semiconductor technologies and silicon-integrated circuits. In particular, the high cutoff frequency of advanced CMOS and Silicon-Germanium (SiGe) bipolar devices allow the integration of millimeter-wave circuits with good high-frequency performance and high integration level at moderate mask costs.
- 15 Dec 2020
Breakfast Bytes: Instruction Decoders: RISC vs CISC

Paul McLellan

In my post The Start of the Arm Era I said that it feels like something significant is changing. There's something Arm-y in the air. Suddenly Arm is faster than all x86 processors except the highest end of AMD's line. But why now? The three b...
- 15 Dec 2020
カスタムIC／ミックスシグナル: Virtuosity: Conserve Power— Virtuoso Power Managerのセットアップ

Custom IC Japan

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso Power Managerの機能と可能性をご紹介します。今後のこのミニ・シリーズの投稿にご注目ください。良い設定を満足のいく結末と間違えないでください - 多くの駆け出しの作家は、本当の物語が始まる準備ができただけのところで物語を終わらせてしまいます。 Stanley Schmidt このミニ・シリーズの最初のブログはすでにお...
- 14 Dec 2020
Digital Design: Voltus Voice: Worried about Fins Getting Self-Heated – Here’s SHE Analysis to the Rescue

sakshin

This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis flow.
- 14 Dec 2020
Life at Cadence: My Life at Cadence: Dimitra Papazoglou

Laura Charabot

Cadence embraces multiculturality and diversity as an important part of our One Team culture. This becomes very clear looking at our offices across the globe and in Europe, where we are proud to count more than 1,000 talented employees coming from ma...
- 14 Dec 2020
Breakfast Bytes: Avoiding PCB Respins with Better Computational Software

Paul McLellan

When I first came to the US, I started at VLSI Technology supporting a project called Bagpipe, mostly by getting the big Versatec plotter that VLSI had purchased to work at full speed and to spool jobs. Bagpipe was a chip for the future Mac...
- 14 Dec 2020
Breakfast Bytes: Sunday Brunch Video for 13th December 2020

Paul McLellan

https://youtu.be/ZcYIbkrHSv4 Made by my Christmas tree (camera Carey Guo) Monday: CadenceCONNECT: Mission Critical - Tom Beckley's Keynote Tuesday: How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs Wednesday: Photonics: How...
- 13 Dec 2020
Life at Cadence: Highlighting Our Girl Geeks at Cadence!

Mary Kasik

Last month, Cadence partnered with Girl Geek X for the first time, hosting a virtual, global event that featured five technical women at Cadence who provided thought leadership on a variety of inspiring topics. This event was a great way to highlight...
- 11 Dec 2020
System, PCB, & Package Design : BoardSurfers: Managing Materials Using A Single Material File for PCB, Package, and Simulation

Sarbjit

Legacy material editors supported different file formats leading to inconsistencies across PCB and package substrate design applications. This drawback due to inconsistency is now overcome by the new Material Editor that uses a ...
- 11 Dec 2020
Breakfast Bytes: HBI, a New Standard to Connect Your Chiplets

Paul McLellan

It is not very well-known how involved Cadence is in establishing standards. Recently, in my post Cadence and Standards...and a New Codec for Your Phone, I wrote about this and about one particular standard, the new EVS (Enhanced Voice Services) code...
- 11 Dec 2020
カスタムIC／ミックスシグナル: Virtuosity: Virtuoso ADE Verifierでの検証 - 信頼性の方法!

Custom IC Japan

数年前、私たちは改善および刷新されたVirtuoso ADE Verifierをリリースしました。その様々な利点に親しんで頂いているに違いないと確信しています。ビデオ、ドキュメント、過去のブログといった様々なチャンネルを通じて既に共有していることを要約すると、Virtuoso ADE Verifierはアナログおよびミックスシグナル設計の実装および要件ドリブン検証により、様々な検証段階でプロジェクトフローを管理するのに役立ちます。これに加え、検証プロジェクトにおいてトップダウン、ボトムアップ、ま...
- 10 Dec 2020
Breakfast Bytes: The 2020 RISC-V Summit

Paul McLellan

The second week of December was RISC-V week, the three-day RISC-V summit (or four if you are a member since Monday was "member day"). Tuesday opened with the keynotes being broadcast live. At least, that was the plan. The video platform pre...
- 10 Dec 2020
RF /マイクロ波設計: μWaveRiders:AWR電磁界シミュレータは設計の成功のために複雑なRF/マイクロ波の構造を解析

RF Design Japan

Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。このシリーズの新しいブログに関する通知を受け取るためには、Su...
- 9 Dec 2020

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