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The India Circuit: Ankita Kanojia: A Story of Grit and Determination

Madhavi Rao

At Cadence, giving back to the communities where we live and work is an integral part of the our culture. Helping others is deeply rooted in our DNA and extending this into our communities is one aspect of how we make a difference in the world. One s...
- 29 Sep 2020
System, PCB, & Package Design : IC Packagers: The Importance of Proper DC Net Identification

Tyler

It may surprise some of you, but I often receive databases in which the power and ground nets are not properly identified. Many times, I get these with questions about slow performance during editing actions in the design or a basic confusion of why ...
- 29 Sep 2020
Breakfast Bytes: NXP Glows in Tensilica HiFi

Paul McLellan

One trend that many people have remarked on, is that neural network inference is moving to edge devices. This means that instead of running on big multicore cloud servers with attached GPUs or FPGAs, the network has to run on something like your smar...
- 29 Sep 2020
カスタムIC／ミックスシグナル: Start Your Engines: ミックスシグナル・シミュレーションを高速化するためのヒント

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。ミックスシグ...
- 28 Sep 2020
Digital Design: What’s inside Joules Graphical User Interface!!

Neha Joshi
Power is HOT and it touches everything and everybody! But we can help with power analysis for your chip!!

Do you want to:

Sneak peek inside the schematic?

Analyze power for various blocks?

Identify the relation of hot cells with RTL?

Explore annotation settings?

Joules RTL Power Solution GUI (Graphical User Interface) helps you to analyze/debug the power estimation/results using several GUI capabilities.

Are you ready…
- 28 Sep 2020
Breakfast Bytes: The CHIPS Alliance

Paul McLellan

On September 17, there was a meeting of the CHIPS Alliance. It was online, of course. In three hours, there were ten presentations. CHIPS is actually an acronym, Common Hardware for Interfaces, Processors, and Systems. The presentations, and The CHIP...
- 28 Sep 2020
Breakfast Bytes: Sunday Brunch Video for 27th September 2020

Paul McLellan

https://youtu.be/EUDdGqdmTUU Made in "the Alps" Monday: Complete RF Solution: Think Outside the Chip Tuesday: The First Decade of RISC-V: A Worldwide Phenomenon Wednesday: The European Processor Initiative Thursday: Should the Government Ad...
- 27 Sep 2020
Breakfast Bytes: CadenceLIVE Europe 2020 Preview

Paul McLellan

Normally, in May, I'd have been off to Unterschleißheim, a suburb of Munich where historically we've held what used to be called CDNLive EMEA. We renamed this CadenceLIVE Europe and pushed it out from its original May dates to Octo...
- 25 Sep 2020
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: クロス・ファブリックな電磁界解析 - IC、パッケージ、ボードのデータをマージするという面倒な作業をなくす

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 24 Sep 2020
カスタムIC／ミックスシグナル: Virtuosity: What's New in Run Plan – パート IV

Custom IC Japan

このブログは、what’s new blogシリーズの一部です。このブログの関連リソースのセクションに、このシリーズの以前のブログへのリンクがあります。ユーザーが最新の設計検証の複雑さを克服できるようにするために、我々はRun Planアシスタントのユーザビリティの改善と改良のために絶え間ない努力を行ってきました。このスペースの投稿で、Virtuoso® ADE AssemblerのRun Planの新たな改善を確認して下さい。 IC6.1.8/ICADVM18.1のVirt...
- 24 Sep 2020
Analog/Custom Design: Virtuosity: Usability Enhancements in Simulation Driven Routing

Parula

Since IC6.1.8 and ICADVM18.1 was released, we have continued our drive to improve the usability of Simulation Driven Routing. Read through this blog to know the key enhancements in this area.
- 24 Sep 2020
Breakfast Bytes: Should the Government Adopt Commercial Best Practice?

Paul McLellan

There is something called Betteridge's Law of Headlines that if a headline or title asks a question, then the answer is "no". I think the title of today's blog post, however, is a definitive "yes". I'm thinking about d...
- 24 Sep 2020
The India Circuit: We Have Winners! … Of The CadenceLIVE 2020 India Best Presentation Award

sangramjena

CadenceLIVE 2020 India, our first digital conference held on 9-10 September and what an event it was! With 75 technical paper presentations, four keynotes, a virtual exhibition area, and fun gamification, CadenceLIVE once again proved to be one of th...
- 23 Sep 2020
System, PCB, & Package Design : BoardSurfers: Create Custom Footprints with ECAD MCAD Library Creator

Sanjiv Bhatia

For every PCB designer, adding correct footprints to the PCB is important. Also, sometimes when you are creating a new project, your client demands a new component to be added to the design for which you do not have a footprint.
- 23 Sep 2020
Breakfast Bytes: The European Processor Initiative

Paul McLellan

At the recent RISC-V Global Forum, one of the presenters was Jean-Marc Denis, chairman of the European Processor Initiative (EPI), or as he described it, the European approach to the exascale age and the road towards sovereignty. The project is drive...
- 23 Sep 2020
カスタムIC／ミックスシグナル: Start Your Engines: AMS UNLで先進のデジタル・テストベンチをシームレスに再利用する

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 UVM (Univer...
- 22 Sep 2020
System, PCB, & Package Design : IC Packagers: Creating Standards-Compliant Packages

Tyler

When you are creating a BGA package component, you are, almost certainly, going to be implementing one that adheres to JEDEC standards. This means selecting from a set of available package size and pin pitch combinations, using a specific, grid-based...
- 22 Sep 2020
Analog/Custom Design: Virtuosity: What’s New on the Cadence Learning and Support Portal – Part 1

Dishika Majumdar

Cadence Learning and Support portal has a RAK series that walks you through a sample design flow, illustrating the use of the Custom IC Virtuoso Platform tools at various design stages. Click here to know more.
- 22 Sep 2020
Breakfast Bytes: The First Decade of RISC-V: A Worldwide Phenomenon

Paul McLellan

A couple of weeks ago was the RISC-V Global Forum. Earlier in the week, I wrote about RISC-V State of the Universe, mostly covering Krste's keynote that was at 8:00am—that is to say, in the middle of the conference! Today, I will cover Dave...
- 22 Sep 2020
Digital Design: A Refresher on the Basics of Timing Analysis and Signoff

FormerMember

Technology is changing the strategies we use to do things - oh so fast that 2010 seems like a distant past- within many spaces -- including the way we do our current topic of interest - Timing Signoff in Digital Implementation. The smaller nodes - le...
- 21 Sep 2020
Digital Design: Voltus Voice: Accelerate Power Signoff and Design Closure with this IR Aware Placement Technology

AndreaBarletta

This blog introduces the Innovus Power Integrity Solution that integrates the Innovus Implementation System and Voltus IC Power Integrity Solution to alleviate signoff bottlenecks and provide faster convergence at the end of the flow.
- 21 Sep 2020
Analog/Custom Design: Start Your Engines: A GUI to Define HDL Packages for the AMS Designer and SystemVerilog Netlister Flows Conveniently

Andre Baguenie

In this post, I will cover how HDL packages in Virtuoso can be set up for use in the AMS Designer flow.
- 21 Sep 2020
Breakfast Bytes: Complete RF Solution: Think Outside the Chip

Paul McLellan

At the recent CadenceLIVE Americas, Cadence's Yuval Shay presented Think Outside the Chip: A Comprehensive RF Flow for IC, Package, and Module Design. Before cellphones and Wi-Fi, radios were not that common, and RF design was even more of a bla...
- 21 Sep 2020
定制IC芯片设计 : Virtuoso Meets Maxwell: Virtuoso RF 解决方案 —让事情变得更简单

kfullerton

我们都听过“少即是多”和“保持简单化“的说法。如果依照这两个建议来运行电磁仿真，用户将会获得巨大收益。在此博客中，我将分享一些与Virtuoso RF 解决方案之图形简化功能相关的经验，在不影响精度的前提下，帮助客户提高其产品性能。
- 21 Sep 2020
Academic Network: Virtual Academic Track at CadenceLIVE Europe 2020 and Master Thesis Awards

Anton Klotz

You might have noticed that Cadence has changed its website, its colours, its message. We have also changed the name of our user conference, what used to be CDNLive EMEA has become CadenceLIVE Europe! Not only did the name of the event change, but a...
- 18 Sep 2020

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