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Analog/Custom Design: Virtuoso Video Dairy : Direct Measurements Assistant in Virtuoso Visualization and Analysis XL

Chandrika Durbha

Ever had to use long expressions just to create simple measurements for plots and waveforms or use markers to measure amplitude, rise, and fall times? That too when these measurements might not even stay in place?

If yes, then read on to find out how you can simplify these tasks.

From IC6.1.8 ISR13 and ICADVM18.1 ISR13 releases, we have introduced the new Direct Measurements assistant in Virtuoso Visualization and Analysis…
- 18 Sep 2020
Breakfast Bytes: Understanding Machine Learning: A Model with One Weight

Paul McLellan

I wrote a post recently, HOT CHIPS: Scaling out Deep Learning Training, which I considered to be an introduction to deep learning training (in the first half) and scaling out (in the second). But even my boss told me it was "meaty" so ...
- 18 Sep 2020
PCB、IC封装：设计与仿真分析: 极致PCB设计全流程 I 最终章：质量设计与检查

SDA China

审视相邻层，避免串扰问题；审视走线层及参考平面，避免信号跨分割；审视每个电源平面，避免通流不足…… 针对SI/PI的检查动作是每位工程师的必修课，通常是在检查环节落实，但是却往往避免不了遗漏，而可能导致信号设计质量问题。最后一期的内容，我们将与大家分享在PCB设计环境下，如何通过In-Design Analysis（IDA，即设计同步分析）来实现信号质量设计，在设计过程中就尽力排除信号质量隐患，从而实现高质量交付。 “极致PCB设计全流程” ...
- 17 Sep 2020
カスタムIC／ミックスシグナル: Virtuoso Video Diary: SKILLでPlotting Templateを操作する方法

Custom IC Japan

MaestroのPlotting Templateがサポートされてからしばらく経ち、ご利用中のお客様も増えているかと思います。これらのテンプレートを使用すると、プロットのカスタマイズを手動で行う際に費やす時間を大幅に削減できることを実感できます。しかし、SKILL関数を使用してこれらのテンプレートを操作してみたことはありますか？操作したことがない場合は、このブログを読んで、これらの関数の詳細を確認してください: maeGetAllPlottingTemplates maeGetAllPlott...
- 17 Sep 2020
Analog/Custom Design: Virtuosity: Smart View Multi-Process Corners in Virtuoso ADE Assembler and Explorer

Arja H

Click here to read the latest blog about the updated 'Using Quantus Smart View in the Virtuoso Analog Design Environment Rapid Adoption Kit'. This not only explains how to set up and simulate with a Smart View, but also discusses how to simulate with multi-process corners defined in the Smart View.
- 17 Sep 2020
Breakfast Bytes: Cadence Triple Gold at the Stevie Awards

Paul McLellan

Do you know what the Stevie Awards are? Officially, they are the International Business Awards, but just like the Academy Awards of Merit are colloquially known as Oscars, these awards are known as Stevies. They are: a set of eight business awards ...
- 17 Sep 2020
Verification: JasperGold FPV: Asynchronous Designs? No Problem!

XTeam

Asynchronous designs happen. They’re not particularly easy to verify, but sometimes they’re necessary. If you don’t have a system clock, or if you have controllers that operate at a high speed with low power dissipation, or even if you do have a system clock but it’s noisy, your design may be asynchronous, and that’s okay. It’s no secret that asynchronous designs are a challenge—so what…
- 16 Sep 2020
Verification: Cadence Is Arm-and-Arm with Arm: Fast Models for Fast Prototyping

XTeam

If you’re not familiar with the Arm/Cadence collaboration, you’ve been missing out. Arm has been using Cadence’s virtual system platform—Palladium® Z1 for emulation and Protium S1 for prototyping—for years, and with these, Arm powers their wide array of fast models for virtual prototyping to make the emulation process even faster than it already is.

Interested?

Well, it’s no secret that…
- 16 Sep 2020
Breakfast Bytes: RISC-V State of the Universe

Paul McLellan

A couple of weeks ago was the RISC-V Global Forum. This was truly global, in that it started at midnight California time and ran for 18 hours until 8:00pm the following evening, with people presenting from their living rooms all over the world. Prese...
- 16 Sep 2020
Digital Design: Join Us for a Deep-Dive into Block Implementation with Innovus Using the Stylus Common User Interface

Attila Zsigmond

If you are looking for a comprehensive training on block implementation with Innovus using the Stylus Common User Interface, look no further. This 3-day training, suitable for both beginner- and advanced designers, will take you through the complete digital block implementation flow, offering a detailed break-down of all implementation steps, while making you familiar with the graphical user interface, commands and attributes…
- 15 Sep 2020
System, PCB, & Package Design : BoardSurfers: Installation Know-How: Which Installation Method is Right for You?

Shikha Jain

Installing new software seems like a daunting task for most of us. You may feel burdened with concerns like how to install and what options to choose, and so on. So, in this post, I will unload your worries and share some best practices to make the i...
- 15 Sep 2020
System, PCB, & Package Design : IC Packagers: Shrinking Dies Inside the Package Layout

Tyler

There are many reasons a die’s size in the package doesn’t match the design size recorded in the IC layout tool. For starters, the IC layout doesn’t always include the scribe lines and other manufacturing offsets/adjustments that do...
- 15 Sep 2020
Breakfast Bytes: PSpice for TI

Paul McLellan

Texas Instruments (TI) is the biggest analog semiconductor company in the world. As it happens, I wrote about TI just two weeks ago in my self-explanatorily-titled post Cadence Wins Texas Instruments' Supplier Excellence Award. I gave...
- 15 Sep 2020
カスタムIC／ミックスシグナル: Start Your Engines: ブログメーターの確認

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 ”ブログメ...
- 14 Sep 2020
Breakfast Bytes: What to Do About IP Developed Before ISO 26262?

Paul McLellan

If you have paid even passing attention to what has been going on in automotive functional safety, then you'll have heard of ISO 26262. You may even know that chapter 11 is the best! That's the one about semiconductors and semicondu...
- 14 Sep 2020
Breakfast Bytes: Sunday Brunch Video for 13th September 2020

Paul McLellan

https://youtu.be/aqlmfd3g5G0 Made in "Jaipur, India" Monday: Labor Day Tuesday: Andrew Kahng and Matthew Morrison on Industry and Academia Wednesday: OIP Ecosystem Forum 2020 Thursday: HOT CHIPS: The Space Race for the Biggest ML Machine Friday: Use ...
- 13 Sep 2020
Verification: Celsius on Protium - Using Cadence Tools to Improve Cadence Tools?

XTeam

The Cadence tool flow is the most comprehensive flow around. If there is an EDA need, you can rest assured that Cadence has a tool that covers that need, and you can be certain that it integrates into the rest of the flow smoothly. In fact, Cadence t...
- 11 Sep 2020
Digital Design: Library Characterization Tidbits: The Perfect Solution for Validating Libraries

HelenShi

A library view contains electrical information that is used throughout design implementation starting from logic synthesis through design optimization to the final signoff verification.
- 11 Sep 2020
Breakfast Bytes: Use Your Imagination to Get Smaller, Faster Chips

Paul McLellan

At the recent CadenceLIVE Americas, Nick Loebner of Imagination Technologies presented Delivering Best PPA on PowerVR GPUs Using Genus/Innovus Digital Implementation System. You probably already know that Imagination Technologies license GPU IP....
- 11 Sep 2020
カスタムIC／ミックスシグナル: Virtuoso Video Diary: 信頼性解析の改善

Custom IC Japan

IC6.1.8/ICADVM18.1 ISR3のVirtuoso® ADE Assembler および Virtuoso ADE Explorer で、信頼性解析の実行方法を完全に変更する、改良されたReliability Options フォームを導入しました。これまで以上に物事をより良くするために、ケイデンスは信頼性解析の改良を続けています。このブログでは、すでに持っているものを再利用するという概念を中心とした2つの機能強化について説明します。ストレス・ファイルの再利用信頼性解...
- 10 Sep 2020
Analog/Custom Design: Virtuosity: Examining Post-Layout Capacitance Using Virtuoso ADE Assembler and ADE Explorer

Arja H

Post-Layout has become a hot topic recently. This has kept me and several other engineers very busy for the past year or so. One of the new, and exciting post-layout features that we have added to Virtuoso ADE Assembler and Virtuoso ADE Explorer is the ability to view the Spectre Classic Simulator netcap report.
- 10 Sep 2020
Breakfast Bytes: HOT CHIPS: The Space Race for the Biggest ML Machine

Paul McLellan

At the recent HOT CHIPS, the Sunday morning tutorial was on scale out of deep learning training. I covered the introduction in my post HOT CHIPS: Scaling out Deep Learning Training. The second half of the morning was devoted to some of the biggest sc...
- 10 Sep 2020
Verification: Mellanox's Tips and Tricks for Maximizing Your Palladium Unit

XTeam

Looking to learn more about the best practices for emulating today’s billion-gate-plus designs? Rest assured—we’ve got you covered.

Cadence has been partnered with Nvidia Mellanox for years, helping them build complete end-to-end solutions for everything from networking to data centers. Mellanox provides and handles every aspect of the process, and they’ve got a long track record of delivering breakthrough…
- 9 Sep 2020
Breakfast Bytes: OIP Ecosystem Forum 2020

Paul McLellan

Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual, the format was similar to the usual. Cliff Hou, Senior Vice President of Technology Development, opened the day with a summary of where everything is in the ecosyst...
- 9 Sep 2020
System, PCB, & Package Design : BoardSurfers: Find by Name or Find by Query - That is the Question!

BarbS

You must be using find utility day in and day out, but if you are unfamiliar with Find by Query in Allegro Layout Editors, read on. Layout editors retained the original Find by Name when developing a new utility to do what Find by Name cou...
- 8 Sep 2020

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