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System, PCB, & Package Design : IC Packagers: Preparing a Completed Package for Mounting on a PCB

Tyler

We’ve covered all the different types of die components and how they interface with the package substrate coming into Allegro Package Designer. But, the package component (whether it’s a BGA, LGA, lead frame, or something else) is destine...
- 8 Sep 2020
Breakfast Bytes: Andrew Kahng and Matthew Morrison on Industry and Academia

Paul McLellan

I attended two presentations on the academic track at the recent CadenceLIVE Americas. The first was Andrew Kahng's presentation A 'Life Cycle' of Teaching and Research on EDA and IC Implementation Methodology. The second was Matthew...
- 8 Sep 2020
定制IC芯片设计 : Virtuoso Meets Maxwell: 当裸片版图没有Bump，有Pad Shapes时，怎么输出裸片版图?

deeptig

如果您的裸片版图不是通过Bumps，而是通过 pad shapes和标签来识别I / O位置，那么您可能会有种无所适从的感觉。因此在这篇文章中，我将为大家介绍一种新的适用于裸片版图的解决方案。
- 7 Sep 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Thinking Outside the Chip--Advantages of Interoperability Between Best-In-Class IC and IC Packaging Design and Verification Tools

danbaldwin

Many of today’s analog, RF, and mixed-signal designs require the integration of multiple ICs across varying substrate technologies to achieve required performance goals. The integration of heterogeneous devices allows designers to achieve results that can’t easily be duplicated using a monolithic IC (SoC) design approach. At the same time, heterogeneous integration introduces a whole new set of challenges for today’s…
- 7 Sep 2020
Breakfast Bytes: Sunday Brunch Video for 6th September 2020

Paul McLellan

https://youtu.be/bj1-b3YpuXg Made in "Costa Rica" Monday: Cadence Wins Texas Instruments' Supplier Excellence Award Tuesday: InspectAR: Augmented Reality in Newfoundland Wednesday: CadenceLIVE India 2020 Preview Thursday:&nbsp...
- 6 Sep 2020
カスタムIC／ミックスシグナル: Virtuosity: 日本の読者に朗報です

Custom IC Japan

最近私たちは、ノートパソコン、スマートフォン、テレビなど、画面の前でほとんどの時間を費やしています。これらのガジェットは、自宅やオンライン・プロジェクト、その他の仕事関連のタスクでの作業を簡単にサポートする、最高の仲間になりました。そして、私たちが余暇に視聴するために利用できる多くの驚くべき魅力的なコンテンツがあることを忘れないで下さい。問題は、テレビ番組で家族のそれぞれの好みが異なるときに発生します。しかし、最近、みんなの注目を集めているという共通のコンテンツが1つあります。...
- 3 Sep 2020
Breakfast Bytes: Labor Day Offtopic: Microroasting Coffee

Paul McLellan

Labor Day is coming up on Monday. Friday is also a Cadence holiday and Breakfast Bytes will not appear. So today is the last post before a holiday, and as always I write about something non-electronic. Today, coffee. Microroasting sounds like somethi...
- 3 Sep 2020
PCB設計／ICパッケージ設計: inspectAR: ニューファンドランドの”拡張現実”（AR）

SPB Japan

先日、CadenceLIVEでのAnirudhの基調講演についてAnirudh's Keynote: A New Product...and an Acquisition で取り上げました。この中でinspectARの買収について言及がありました。もっと詳しい話を聞くため、私はCEOのMihir Shahにコンタクトを取りました。最初の驚きは、同社がカナダのニューファンドランドを拠点としていることです。インド同様に、ニューファンドランドも1時間単位ではないタイムゾーンを採用する地域の1...
- 2 Sep 2020
System, PCB, & Package Design : BoardSurfers: Implementing SKILL Code

Rachna2018

This post is in continuation of Extending Allegro Layout Capabilities with SKILL, where I described how SKILL code can make things faster and more efficient even without having to code from scratch. In this post, we’ll see sample implementations...
- 2 Sep 2020
Breakfast Bytes: CadenceLIVE India 2020 Preview

Paul McLellan

In a normal year, I would already have my plane ticket to fly to Bangalore for CadenceLIVE India. It's an insane trip, in some ways, with about 40 hours of travel to attend about 16 hours of the actual event spread over two days. Of course, ...
- 2 Sep 2020
Verification: Xcelium ML: The Next Big Thing in Regression

XTeam

Looking for that extra kick in your regression performance? Cadence’s Xcelium Logic Simulator has a new feature just for you. Harnessing the power of machine learning, which is one of the areas of computational software innovation, Xcelium ML is here to help you optimize your regressions.

The inherently iterative, data-driven nature of simulation seems ripe for a machine-learning assisted tool, and Xcelium ML is here to fill…
- 1 Sep 2020
System, PCB, & Package Design : IC Packagers: How Die Stacking Works in Allegro Package Designer

Tyler

Recently, we’ve covered some basics about why imported dies default to chip-down flip-chips and even the different types of mirroring. To close on the topic of dies, die stacks, and the interaction of components why may interface together witho...
- 1 Sep 2020
Breakfast Bytes: InspectAR: Augmented Reality in Newfoundland

Paul McLellan

I covered Anirudh's CadenceLIVE keynote in my post Anirudh's Keynote: A New Product...and an Acquisition. The acquisition mentioned was InspectAR. I contacted Mihir Shah, the CEO, to find out more. The first surprise is that the company is based in N...
- 1 Sep 2020
PCB設計／ICパッケージ設計: TSMC: スペシャルティープロセスとスペシャルティーパッケージング

SPB Japan

先週の月曜日に、TSMC Technology Summit 2020がありました。もちろん、バーチャルでの開催です。それについては、別稿のTSMC Technology Symposium: All the Processes, All the Fabs(*英語)で取り上げました。今回の記事はスペシャルティープロセスとアドバンスドパッケージについてで、これはTSMCでは3DFabricという名称が使われているものです。スペシャルティーテクノロジー Kevin Zhangがスペシャルティー...
- 31 Aug 2020
Digital Design: Voltus Voice: Tempus Power Integrity Solution - Find Those Needles in the Haystack Quickly!

Jerry Zhao

This blog introduces the Tempus Power Integrity Solution that integrates the Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution signoff engines to find silicon performance failures missed with traditional IR analysis.
- 31 Aug 2020
Digital Design: Use the Industry’s Leading Digital Implementation Flow from inside Virtuoso with a Package Sized and Priced Perfect for Your Next Mixed Signal Project!

MJ Cad

Hi Everyone, Does the idea of using the best digital implementation tools on the market for your block sound interesting to you, but the full capacity is overkill, setup too daunting, or costs too high? If the answer is yes, do not worry; Cadence has...
- 31 Aug 2020
Verification: The Best Way to Learn SystemVerilog Accelerated Verification with UVM – Blended Training

SAIKAT SANA

UVM is a heavily used, standard, proven, easy-to-use, automated verification methodology in our current industry. With the growing use of UVM methodology, engineers need to have an in-depth knowledge. For someone getting started with UVM, it can be challenging and a steep learning curve. So, we offer a comprehensive and adaptable course SystemVerilog Accelerated Verification with UVM to sharpen your UVM skills.

This course…
- 31 Aug 2020
Breakfast Bytes: Cadence Wins Texas Instruments' Supplier Excellence Award

Paul McLellan

I attended the online ceremony recently in which Texas Instruments (TI) formally awarded Cadence their Supplier Excellence Award. It is the first time ever that this award has gone to an EDA/IP company. The award itself is a heavy piece of glass...
- 31 Aug 2020
カスタムIC／ミックスシグナル: Virtuosity: トレースの特定

Custom IC Japan

近年、実行する必要があるシミュレーション数が増えることで、プロットの数が膨大となり、各プロットが、どのCadence® Virtuoso® ADE XL、 Virtuoso® ADE Assembler または Virtuoso® ADE Explorer の履歴、テスト、またはコーナーに属しているかを理解するのが困難になっています。こういった問題に対応するために、IC.6.1.8/ICADVM18.1の、Virtuoso® Visualiza...
- 31 Aug 2020
PCB設計／ICパッケージ設計: BoardSurfers: Allegro In-Design Crosstalk Analysis：PCBキャンバスでシグナルインテグリティシミュレーション

SPB Japan

クロストークとは”アグレッサー”ネットから”ビクティム”ネットへの不要な信号の転送であり、PCB設計で生じる可能性のあるシグナルインテグリティ（SI）問題の中でも主要なものの1つです。クロストークを可能な限り低減することは、PCB設計にとって常に重要です。多くの場合、専用ツールを使用したクロストーク解析の実行には、専門知識が求められ、またドライバー／レシーバーモデルの詳細についての理解も必要とされる、時間の掛かる作業となります。 Allegro&r...
- 30 Aug 2020
Breakfast Bytes: Sunday Brunch Video for 30th August 2020

Paul McLellan

https://youtu.be/IwA132i-R80 Made in "an aquarium" Monday: Under the Hood of Xcelium ML Tuesday: Cadence Certified on TSMC N3, Ultralink on N6, and 3DFabric Wednesday: HOT CHIPS Server and Laptop Processors: Intel, AMD, IBM, Marvell Thursday: TS...
- 30 Aug 2020
Breakfast Bytes: TSMC: Specialty Processes and Specialty Packaging

Paul McLellan

Last Monday was the TSMC Technology Summit 2020. Virtual, of course. I covered that in my post TSMC Technology Symposium: All the Processes, All the Fabs. Today it is the turn of specialty processes and advanced package, for which TSMC now uses ...
- 28 Aug 2020
Digital Design: Library Characterization Tidbits: Accelerating Signoff with Liberate - Installation and Licensing - Part 1

AbhaRawat

With this blog starts a mini-series in Library Characterization Tidbits to share insights into the questions that our customers frequently ask. In this first edition, read about questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.
- 27 Aug 2020
Analog/Custom Design: Virtuosity: In the Line of Veri-Fire - Episode 5

Team ADE Verifier

Welcome to the fifth episode of the Veri-Fire series. Check out the new questions and answers that we have for you!
- 27 Aug 2020
System, PCB, & Package Design : BoardSurfers: Extending Allegro Layout Capabilities with SKILL

Rachna2018

Why do I need SKILL? The difference between generic departmental store clothing and premium custom tailoring is what the effective use of SKILL scripts can bring to your PCB Layout design world. While our layout applications come loaded with power-packed features...
- 27 Aug 2020

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