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Life at Cadence: The Returnship Journey: Part 3

Ale Costa

Madhu Comandur's Journey Returnship programs are essential in helping professionals restart their careers after an extended break. According to a study by the ManpowerGroup, 84% of millennials—both men and women—say they anticipate &l...
- 26 Aug 2020
Breakfast Bytes: HOT CHIPS Server and Laptop Processors: Intel, AMD, IBM, Marvell

Paul McLellan

At the recent HOT CHIPS, the first day was dedicated to general-purpose processors, and the second day to special-purpose processors. Today, I'm going to take a look at some of the processors presented on the first day. If we look at server chips, th...
- 26 Aug 2020
System, PCB, & Package Design : IC Packagers: Establishing Connectivity Between Die and BGA

Tyler

The BGA component serves the primary role of redistributing the signals from the die it protects to an interface pattern (the BGA’s balls) compatible with the host PCB it mounts on. As a result, many IC package designs are among those who do no...
- 25 Aug 2020
Analog/Custom Design: Virtuosity: Do Rulers Rule Your Layout Designs?

KomalJohar

You can now use the segment mode, Auto, while creating the ruler. This feature lets you create multiple rulers in just two clicks.
- 25 Aug 2020
Breakfast Bytes: Cadence Certified on TSMC N3, Ultralink on N6, and 3DFabric

Paul McLellan

Yesterday was it TSMC Technology Symposium. Normally this would have been held face-to-face in April but, like everything else, it has gone virtual. Today, it is the OIP Ecosystem Forum. As usual, Cadence is making some TSMC-related announcement...
- 25 Aug 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Unified Libraries — Making Way For Cross-Platform Flows

deeptig

Heterogeneous integration of components using different process technologies can appear to be magic! It mitigates the high cost of homogeneous system-on-chip (SOC) integration by allowing designers to combine proven designs, which use older nodes, on substrates by using newer process technologies. Traditional outsourced assembly and test (OSAT) vendors and IC vendors are competing to provide integration methodologies…
- 24 Aug 2020
Breakfast Bytes: Under the Hood of Xcelium ML

Paul McLellan

At the recent CadenceLIVE Americas, Yosinori (Yoshi) Watanabe presented what he titled Accelerate Regression Performance with Machine Learning. He had to give it such an anodyne title since it appeared in the agenda before the product had b...
- 24 Aug 2020
Breakfast Bytes: Sunday Brunch Video for 23rd August 2020

Paul McLellan

https://youtu.be/LIKlevqCB-U Made in front of my TV (camera Carey Guo) Monday: Alberto's Keynote: Cadence and Academia Tuesday: Climbing Annapurna to the Clouds Wednesday: Thermal Analysis of Protium X1 Thursday: HOT CHIPS: Scaling out Deep ...
- 23 Aug 2020
PCB、IC封装：设计与仿真分析: Sigrity Aurora：融合Allegro用户体验与Sigrity强大功能，为工程师提供设计同步分析

Sigrity

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章 “Sigrity Aurora: In-Design Analysis“。 space Cadence最新发布的Sigrity Aurora工具将Allegro®用户体验与Sigrity引擎的强大功能相结合。借助这项新工具，设计团队能够在Allegro单一环境中实现：初步探索、设计、仿真分析、最终验证和签...
- 22 Aug 2020
Academic Network: Custom IC, Analog, and RF Design Training Deep Dive: Part 4

Kira Jones

Welcome to the fourth and final part of the Custom IC, Analog, and RF Design Online Training deep dive blog series. In parts one, two, and three, we’ve covered a variety of tools including Virtuoso, Spectre Simulation, Xcelium mixed-signal opti...
- 21 Aug 2020
Digital Design: Pegasus Verification System Product Page is Live!!!

Sarita Sharma

We are excited to share that PegasusTM Verification System Product page is now live on Cadence Online Support site. This page is the one-stop destination where you will get all PegasusTM related information. Here is the glimpse of the page: Let&rsqu...
- 21 Aug 2020
Breakfast Bytes: Anirudh's Keynote: A New Product...and an Acquisition

Paul McLellan

Anirudh Devgan, Cadence's President, gave the keynote to open the second day of CadenceLIVE Americas. He titled it Computational Software for Intelligent System Design. To avoid duplication, in this blog post I'm not going to talk about two&n...
- 21 Aug 2020
System, PCB, & Package Design : 2019 HF2 Release for Clarity, Celsius, and Sigrity Tools Now Available

SigrityReleaseTeam

The 2019 HF2 production release for Clarity, Celsius, and Sigrity tools is now available for download at Cadence Downloads. SIGRITY2019 HF2 For information about supported platforms, compatibility with other Cadence tools, and details of key...
- 20 Aug 2020
Analog/Custom Design: Virtuosity: What's New in Run Plan - Part IV

Yagya Mishra

Click here to view our latest blog in the What's New in Run Plan blog series that discusses the enhancements added to the Run Plan assistant across different Virtuoso ADE Assembler IC6.1.8/ICADVM18.1 ISR releases.
- 20 Aug 2020
Breakfast Bytes: HOT CHIPS: Scaling out Deep Learning Training

Paul McLellan

The annual HOT CHIPS conference took place on August 17-18. Of course, it was virtual. As always, on the Sunday before there were two half-day tutorials. In the morning, it was on scaling deep learning training. In this context, "scaling" m...
- 20 Aug 2020
Analog/Custom Design: Virtuoso Video Diary: The SKILLed Way of Using Plotting Templates

Udit Rajput

Read through this blog to know more about how to use the maeGetAllPlottingTemplates, maePlotWithPlottingTemplate, and maeSaveImagesUsingPlottingTemplate SKILL functions to work with maestro plotting templates.
- 20 Aug 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: How to Run a RAVEL Rule from the GUI

Shreyansh

With the current scenario of COVID-19, you cannot do without rules. You have to soak vegetables in brine for ten minutes, wash milk in plastic packaging with soap, sanitize metals with an alcoholic solution (70% and above), and whatnot. Well, you get...
- 19 Aug 2020
Breakfast Bytes: Thermal Analysis of Protium X1

Paul McLellan

There's a phrase in software development "eat your own dogfood". In fact, there's even an ugly verb "dogfooding". This means using your own software for real. If, say, you are developing a source-code management system (al...
- 19 Aug 2020
Analog/Custom Design: Virtuoso IC6.1.8 ISR13 and ICADVM18.1 ISR13 Now Available

Virtuoso Release Team

The IC6.1.8 ISR13 and ICADVM18.1 ISR13 production releases are now available for download.
- 19 Aug 2020
System, PCB, & Package Design : IC Packagers: Designing a Package from the Flip-Chip’s Perspective

Tyler

Most package substrates are designed as they will be placed onto the host PCB if the package were mounted on the top side. This means that the BGA’s balls are on the bottom layer of the cross-section. Your dies are mounted on the top. For wire ...
- 18 Aug 2020
Breakfast Bytes: Climbing Annapurna to the Clouds

Paul McLellan

One of the keynotes at last week's CadenceLIVE Americas 2020 was by Nafea Bshara. He is a VP/Distinguished Engineer at Amazon, working on system/hardware/silicon products for AWS infrastructure. But perhaps more importantly, he joined AWS in 2016 whe...
- 18 Aug 2020
カスタムIC／ミックスシグナル: Virtuosity: 古いADEのstateやviewをADE ExplorerまたはADE Assemblerで開く

Custom IC Japan

Virtuoso ® ADE L stateやVirtuoso ® ADE XL viewを開くとき、デフォルトのアプリケーションが、以前の古いADE LまたはXLにセットされていることが面倒だと感じた事はありませんか？すでにVirtuoso ® ADE AssemblerやVirtuoso ® ADE Explorerに移行済みである場合、Open Fileダイアログで指定されているアプリケーションをADE ExplorerやADE As...
- 17 Aug 2020
Breakfast Bytes: Alberto's Keynote: Cadence and Academia

Paul McLellan

On the last day of CadenceLIVE 2020, there was a keynote by Alberto Sangiovanni-Vincentelli. Just in case it wasn't obvious from his name that he's Italian, he delivered the keynote from his villa on the Mediterranean coast near Rome. He titl...
- 17 Aug 2020
定制IC芯片设计 : Virtuoso Meets Maxwell: Bumps, Bumps……如何找到Bumps？

Brian LaBorde

Bumps对Virtuoso MultiTech Framework解决方案来说至关重要, 它提供了堆叠芯片，中介层，封装和电路板两两间的连接。 Bump的位置，连接性和其他属性都是创建TILP的基础，我们将这些属性结合以生成系统级版图。 ”Virtuoso Meets Maxwell “是一系列旨在探讨Virtuoso RF 和Virtuoso MultiTech现有及潜在功能的博客。Virtuoso又是如何与麦克斯韦方程组(Maxwell)联系上的呢? 当前版本的Virtuoso 支持射频设计，设计工程师们使用麦克斯韦方程组，就能测量物理和辐射效应。该系列博客除了提供一些实用软件和增强功能的精辟见解外，还能通过播客的方式，与听众分享博主和专家们在使用Virtuoso Pack...
- 16 Aug 2020
Breakfast Bytes: Sunday Brunch Video for 16th August 2020

Paul McLellan

https://youtu.be/7W55PNo-SoI Made in "CadenceLIVE Lounge" (camera me) Monday: 120th Anniversary of Hilbert's Problems Tuesday: Cadence Executives on Computational Software Wednesday: Xcelium ML: Black-Belt Verification Enginee...
- 16 Aug 2020

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