Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Breakfast Bytes: CadenceLIVE 2020: As It Happened

Paul McLellan

CadenceLIVE 2020 Americas took place virtually earlier this week, spread across Tuesday, Wednesday, and Thursday. First, there were close to 2,000 attendees. Since this was a virtual conference, it's not fair to compare that number to last year ...
- 14 Aug 2020
Analog/Custom Design: Virtuosity: In the Line of Veri-Fire - Episode 4

Team ADE Verifier

Want to know what's new in this episode of Veri-Fire? Check it out!
- 13 Aug 2020
Breakfast Bytes: Computational Logistics

Paul McLellan

General Omar Bradley famously said: “Amateurs talk strategy. Professionals talk logistics.” And Napoleon (perhaps) said "An army marches on its stomach". That's not to underestimate other aspects of armies, such as...
- 13 Aug 2020
Academic Network: Custom IC, Analog, and RF Design Training Deep Dive: Part 3

Kira Jones

Welcome to part 3 of the Custom IC, Analog, and RF Design Online Training deep dive blog series. Part 3 will be building off the skills learned in Part 1 and Part 2 so be sure that you are familiar with those tools and technologies before beginning t...
- 12 Aug 2020
Breakfast Bytes: Xcelium ML: Black-Belt Verification Engineer in a Tool

Paul McLellan

What if I told you I knew someone who could improve your regression efficiency: make fewer runs, spend less runtime on the runs you do make, and have the same coverage at the end? You'd say that he or she sounds like a great verification e...
- 12 Aug 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Magic! – Dynamic Voiding in Virtuoso RF Solution

skai

While SiP Layout Option is – and continues to be – one of the most complete solutions for package design, the Virtuoso RF Solution gives access to a constantly increasing set of package layout authoring capabilities inside the Virtuoso Layout Suite. Having both IC and package inside the same design platform enables Virtuoso users to do package layout in their preferred design environment. An innovative co-design environment…
- 11 Aug 2020
System, PCB, & Package Design : BoardSurfers: Allegro In-Design Crosstalk Analysis: Signal Integrity Simulations on the PCB Canvas

Shirin Farrahi

Crosstalk is the transfer of unwanted signals from an “aggressor” net to a “victim” and is one of the major classes of signal integrity (SI) problems that can exist in Printed Circuit Board (PCB) designs. Reducing crosstalk as...
- 11 Aug 2020
System, PCB, & Package Design : IC Packagers: Make Acute Angles a Sharp Problem of the Past

Tyler

Sharp angles, whether they create a spike in a poured shape or form an acid trap between two different pieces of metal, are a problem for us all. And as designers, we will go out of our way to try and avoid creating these situations; they will still ...
- 11 Aug 2020
Breakfast Bytes: Cadence Executives on Computational Software

Paul McLellan

CadenceLIVE starts today, Tuesday, August 11, and runs through Thursday. One thing that I know some of the keynotes will cover will be computational software, a name for many of the sorts of algorithms that underlie EDA and system design tools....
- 11 Aug 2020
カスタムIC／ミックスシグナル: Virtuosity: Multi-Technology Simulation (MTS)の実行方法は？

Custom IC Japan

マルチ・テクノロジ・シミュレーション(Multi-Technology Simulation; MTS)をVirtuoso® ADE ExplorerとVirtuoso® ADE Assemblerで実行する方法を示したハンズオン型の資料をお探しですか？今日の急速にシュリンクしているテクノロジでは、カスタムICシステム・イン・パッケージ(System-in-Package; SiP)を設計する機会が増えています。しかし、ここで課題となるのが、異なるテクノロジを使用してこれらの...
- 11 Aug 2020
Digital Design: Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric Protection Scheme

Vijetha

This blog highlights the key capabilities and benefits of the Voltus ESD analysis flow.
- 10 Aug 2020
Breakfast Bytes: 120th Anniversary of Hilbert's Problems

Paul McLellan

The computational software algorithms used in EDA are fundamentally mathematical in nature. Many algorithms are various forms of computation using very large sparse matrices. Last Saturday was a significant anniversary in the foundations of mathemati...
- 10 Aug 2020
PCB、IC封装：设计与仿真分析: 电子系统设计中进行片上热分析的四大挑战与应对

SDA China

在大约 138 亿年前的创生之初，我们的宇宙在 0 到 10-43 (10^(-43))秒的短短时间里产生和释放了大量的热量或能量，这在理论上得到了各种模型和测量数据的支持。自那以后，宇宙中各种各样的物理机制一直推动着能量不断转化为其他形式或者转化回热量，大到太阳中的核聚变，小到电子设备中计算机芯片上微型晶体管的自发热。而为了让每个系统都运行良好，无论是像病毒一样的活体，还是像智能手机一样的人造设备，工作温度范围都是与系统敏捷性息息相关的最重要因素之一。因此，在能量输入和输出的各种预期条件下，能...
- 9 Aug 2020
Breakfast Bytes: Weekend Update 2

Paul McLellan

This is my second update post where I cover things that I have covered before, and where there is some news, but no enough to make a completely new post. The first update was Weekend Update. Cerebras Wafer Scale Engine I wrote about the Cerebras Wafe...
- 7 Aug 2020
Breakfast Bytes: Rigid-Flex

Paul McLellan

Rigid-flex sounds like something that might be a Crossfit workout-of-the-day. But it is actually a way of doing electronic design for small form factors using flexible PCBs (typically along with some normal rigid PCBs too). But they require additiona...
- 6 Aug 2020
Breakfast Bytes: Why Attend CadenceLIVE Americas?

Paul McLellan

We renamed our user conference to CadenceLIVE (from CDNLive) just in time for it not to be live and to go virtual. The first conference is CadenceLIVE Americas coming up from August 11th to 13th. Registration is now open. This is a global event. Comi...
- 5 Aug 2020
PCB設計／ICパッケージ設計: BoardSurfers：17.4-2019 HotFix 007 for Electrical CAD-Mechanical CAD Library Creator について

SPB Japan

Library Creator 17.4-2019 HotFix 007のアップデートより、Templatesダイアログ全体に改良が加えられ、テンプレートを見つけて選択しやすくなりました。また、Propertiesウィンドウに多くの変更が加えられました。もう1つの注目すべき変更は、新しいルールをすばやく追加できるいくつかのボタンをConfigurationダイアログに追加したことです。ここから、変更の詳細についてご紹介します。ルールとコンストレイントを簡単に追加できます。ダイアログに新...
- 4 Aug 2020
PCB設計／ICパッケージ設計: 2020年5月リリース、OrCAD / Allegro 17.4-2019 HotFix 007 の新機能ハイライト

SPB Japan

OrCAD® 及び Allegro® のHotFix 007 (QIR 1)がCadence Downloadsからダウンロードできます。この新リリースでは、数多くの機能の改善や強化が行われており、その多くはお客様からのご要望、ならびに、我々が継続的に追求している使い易さとユーザーエクスペリエンスの向上というフォーカスに基づくものです。このリリースは、スプラッシュ画面においては”2020”と示されます。この最新バージョンを使い始めてみると、いたる所でちょ...
- 4 Aug 2020
System, PCB, & Package Design : BoardSurfers: Installation Know-How: Six Things You Need to Know Before Installing Cadence OrCAD and Allegro Products on Windows

Shikha Jain

Installation of software applications depends upon certain factors such as system configuration, the number of files getting installed, and network speed. Installation time is influenced by a change in any of these elements and hence individual...
- 4 Aug 2020
System, PCB, & Package Design : IC Packagers: Removing and Replacing an Area of a Design

Tyler

If you ever have the need to remove an area of your design, you may find it to be a more complex process than you would think. Shapes in that area will, if you select them with show element, want to pick up the entire shape. That may extend well outs...
- 4 Aug 2020
Breakfast Bytes: Accellera Functional Safety

Paul McLellan

This is my last post about DAC 2020. During DAC Accellera had a workshop about functional safety. In case you don't know, Accellera has a relatively new working group (WG) on Functional Safety. The chair is Cadence's Alessandra Nardi, who coi...
- 4 Aug 2020
Academic Network: Custom IC, Analog, and RF Design Training Deep Dive: Part 2

Kira Jones

Let’s continue exploring the training courses related to Custom IC, Analog, and RF Design. We’re going to be introducing some new courses and some new tools in these training recommendations. It is recommended that you start with Custom I...
- 3 Aug 2020
Breakfast Bytes: DAC 2020: Chips in 2030

Paul McLellan

In 2015, soon after I rejoined Cadence, I went to IEDM, the International Electron Devices Meeting. That year it was in Washington DC. I paid for most of the trip myself since I'd already booked the flights and hotels months in advance to get goo...
- 3 Aug 2020
カスタムIC／ミックスシグナル: Virtuosity: Analog Design Environmentにおけるポストレイアウト関連の機能強化トップ３

Custom IC Japan

今日のブログでは、ポストレイアウトフローの最新の機能強化について説明します。これらの機能強化により、回路図とポストレイアウトの名前のマッピング、端子電圧のプロット、DSPFファイルのスイープなど、長年の問題の多くが解決されます。このブログは、Virtuoso®ADE Assembler、Virtuoso®ADE ExplorerおよびVirtuoso® Visualization and Analysisのリリースされたばかりの機能をカバーするために、週に2回（火曜日と...
- 2 Aug 2020
Analog/Custom Design: Virtuoso Meets Maxwell: How Come There is No Mention of Wirebonded ICs?

Steve PDK Lee

Hello and welcome to Virtuoso Meets Maxwell. If you are a regular reader you might be thinking to yourself, “There’s not a lot about wirebonds in the Virtuoso RF Solution and I’m interested in wirebond support.” That’s a great observation and it’s time for bringing wirebonds into the spotlight.
- 2 Aug 2020

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.