Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

PCB、IC封装：设计与仿真分析: Ken的博客系列之六 | 千兆位串行链路接口的SI方法

Sigrity

作者：Ken Willis 上一篇：高效的互连提取使用IBIS-AMI模型进行仿真此时，SerDes元器件供应商应该已经提供了所需的IBIS-AMI模型，如果这些模型可用，那么替换仿真测试平台中的对应模型。现在，我们重点关注后仿真的验证工作。在仿真测试平台中替换为你自己的模型，尽管这时看起来你好像就马上可以进行仿真工作了，但是对于IBIS-AMI模型仍然有许多工作需要做。如前所述，算法部分或者IBIS-AMI模型的“AMI”部分为SerDes的均衡功能。在双沿数据速...
- 13 Sep 2019
Breakfast Bytes: Intelligent System Design

Paul McLellan

Yesterday in my post Intelligent Systems, I wrote about how the imperative for differentiated products, especially at the high end of markets, is pushing both system and semiconductor companies to take a more holistic view of system design. Cadence c...
- 13 Sep 2019
Breakfast Bytes: Intelligent Systems

Paul McLellan

Cadence's goal is to empower engineers at semiconductor and systems companies to create innovative, intelligent, and highly differentiated electronic products that transform the way people live, work, and play. One big change is for system companies ...
- 12 Sep 2019
Digital Design: Safety and Aging in IoT Devices: What We Know Today

XTeam

How do we achieve highly accurate aging data models for critical circuits in automotive or IoT applications? IoT device aging isn’t well understood yet, since most of it is still so new. How will the software stand up against tomorrow’s t...
- 11 Sep 2019
定制IC芯片设计 : Virtuosity: Spring-Cleaned Virtuoso Doc Closet

Rishu Misri Jaggi

如需了解IC6.1.8 和ICADVM18.1相关的最新文档，请继续阅读.
- 11 Sep 2019
Breakfast Bytes: EDPS Preview 2019

Paul McLellan

EDPS, the Electronic Design Process Symposium, is coming up next Monday. It will be on Thursday, October 3 and Friday, October 4. Once again it will be held at SEMI's offices in Milpitas. I think of it as Gary Smith's conference, since he was al...
- 11 Sep 2019
Life at Cadence: How to Land a Job at Cadence: Recruiters Share Their Best Tips for Standing Out and Getting an Interview

Ashley Sneathen

As we send off the last of our 2019 Summer Interns (read more about their experience here) and say goodbye to summer, our recruiting team is already turning their attention to finding the next group of college hires and interns to join the Cadence te...
- 10 Sep 2019
System, PCB, & Package Design : IC Packagers: How Far Away are You?

Tyler

Layout design is all about clearances. Daily challenges come from maintaining consistent space between your differential pair members, calculating the number of routing channels you can squeeze between two vias, or ensuring adequate clearance of bond...
- 10 Sep 2019
System, PCB, & Package Design : BoardSurfers: PCB Electronics - Electrical Constraints

mrigashira

Whether it's NASA's space missions or a school camping trip; building a cutting-edge, reusable rocket system or baking a simple lemon tart - planning is a must to avoid disasters, or at least to get a predictable output. So is the case with PCBs. You want to plan ahead to avoid design mistakes that can cost you money and time. And that's where constraints come handy.
- 10 Sep 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR6 and ICADVM18.1 ISR6 Now Available

Virtuoso Release Team

The IC6.1.8 ISR6 and ICADVM18.1 ISR6 production releases are now available for download.
- 10 Sep 2019
Breakfast Bytes: CDNLive India 2019: NXP and More

Paul McLellan

Last week I covered Day 1 of CDNLive India. Today it is the turn of verification and PCB/system. With a digression to India's unusual time zone. Day 2 On Thursday, August 29, there were tracks for Advanced Verification Methodology, Performan...
- 10 Sep 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Add Some MAGic to Your ElectroMAGnetic Analysis

kfullerton

If you’ve ever seen a great magician at work, you know that their talent lies in making the impossible look easy. That’s what we have done with Electromagnetic (EM) Analysis in the Virtuoso RF Solution. If you have struggled with cumbersome EM integrations in the past, read further to know what new we have in store for you.
- 9 Sep 2019
Breakfast Bytes: HOT CHIPS: In-DRAM Compute

Paul McLellan

Something that has been discussed for years is the fact that we could add processors to DRAM memory pretty cheaply if we could work out what to do with them. Usually, when people suggest this, they don't really think it through. They are assuming...
- 9 Sep 2019
Verification: Dimensions to Verifying a USB4 Design

Neelabh

Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled…
- 8 Sep 2019
Breakfast Bytes: Sunday Brunch Video for 8th September 2019

Paul McLellan

https://youtu.be/AvimlRMDZng Made at Cadence parking lot (camera Steve Brown) Monday: Labor Day Tuesday: HOT CHIPS: The Tesla Full Self-Driving Computer Wednesday: Conformal Litmus Thursday: Ten Reasons to Attend CDNLive Israel Friday: CDNL...
- 8 Sep 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之五 | 千兆位串行链路接口的SI方法

Sigrity

作者：Ken Willis 上一篇：启用约束驱动设计高效的互连提取一旦物理layout完成（或者至少串行链路差分对的布线完成），就可以进行布局后验证。需要决定使用多大的带宽进行模型提取。为了评估这一点，需要考虑通过链路传递的信号。 PCI Express Gen 4的规格是指上升时间约为22ps，测量值为10%至90%。将上升时间与信号带宽相关联的经典表达式是： BW (GHz) =350 / Trise (ps) 对于PCI Express Gen 4来说，我们首先考虑的是至少16 GHz...
- 6 Sep 2019
Breakfast Bytes: Pervasive Intelligence

Paul McLellan

The biggest change in technology over the last five or ten years is the sudden kicking into gear of artificial intelligence. I'm sure that you are aware of this. Many people have pointed out that there has been more development in the field since...
- 6 Sep 2019
Breakfast Bytes: CDNLive India 2019: Mediatek and More

Paul McLellan

If you live in California, as I do, then India is a long way away. It is 11½ hours time difference, for a start. Air India has a direct flight from San Francisco to New Delhi (over 16 hours) but since CDNLive is in Bangalore, that is not ...
- 6 Sep 2019
Analog/Custom Design: Virtuosity: Support for Stacked Devices in Modgen

Aneesh Shastry

This blog provides an overview of the support for stacked devices in Modgen. This feature makes it easy for you to visualize and edit devices in highly-complex designs, which, in turn, helps achieve higher circuit performance goals in advanced node PDKs. Read the blog post to know more about how to work with stacked devices in Modgen.
- 6 Sep 2019
Academic Network: Cadence and the Academic Network Support Design Contests in the Asia Pacific

Tracy Zhu

Design contests are a unique way for students to get hands-on experience using Cadence® tools, while in a fun and competitive environment. It is important to the Cadence Academic Network to support design contests so that we can help the nex...
- 5 Sep 2019
Breakfast Bytes: Ten Reasons to Attend CDNLive Israel

Paul McLellan

CDNLive Israel is coming up later this month on September 18 at the David Intercontinental in Tel Aviv. I will be attending as usual so you can expect some Breakfast Bytes posts later in the month. 1. A Day Dedicated to Your Interests As al...
- 5 Sep 2019
Breakfast Bytes: Conformal Litmus

Paul McLellan

One of the earliest science experiments I can remember doing was crushing red cabbage in a mortar and pestle with some sort of alcohol. The resulting purple liquid would turn red in acid and blue in alkali. True litmus is not extracted from red cabba...
- 4 Sep 2019
System, PCB, & Package Design : BoardSurfers: PCB Electronics - Component Placement - Get Set and Go!

mrigashira

How do you place components on a PCB design? Manually? Or quickly using automation? Is there a way to rotate or mirror components while placing them? Is there a way to determine the congested areas or the flow within blocks even while placing components? How do you ensure the placed components are aligned? How o you verify all is well with the board? Read on for the answers.
- 3 Sep 2019
System, PCB, & Package Design : IC Packagers: Manufacturing Cross-Hatched Shapes

Tyler

If you use cross-hatched shapes in your package design, you are doubtless aware of some considerations. Namely, if your shape outline is anything but a rectangular outline at a multiple of the hatch line width pattern, and unless it has no objects to...
- 3 Sep 2019
Breakfast Bytes: HOT CHIPS: The Tesla Full Self-Driving Computer

Paul McLellan

On April 22, Tesla held its Autonomy Day. They announced their "Self-Driving Computer" or SDC. (You can read my post from back then in my post Tesla Drives into Chip Design.) I have said several times over the years that I expected that t...
- 3 Sep 2019

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.