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Analog/Custom Design: Virtuoso Video Diary: Can I Put Sticky Notes on Nets When Resolving EM Violations?

NamrataM

Do you know the Virtuoso Electrically Aware Design flow provides a sticky notes-kind of feature called point-to-point info balloons. These info balloons provide critical information that you would find handy while working with critical nets to resolve EM violations. Read more...
- 7 Jun 2019
Breakfast Bytes: 1984 Was Published 70 Years Ago

Paul McLellan

If you work in any aspect of tech, one book that you have to have read is George Orwell's 1984. Aspects of the impact of technology on life are always being compared to things in the book. For example, Big Brother watches everyone through TV scre...
- 7 Jun 2019
Academic Network: Cadence Academic Network Expands to Kazakhstan

Anton Klotz

Dear reader, may I ask you, what do you know about Kazakhstan? Do you know that Kazakhstan is the 9th largest country on earth? I It is nearly four times the size of Texas. Do you know that it is between China and the European part of Russia? Kazakhs...
- 6 Jun 2019
Breakfast Bytes: DAC Wednesday: Verification Lunch, Books, and Bagpipes

Paul McLellan

For my coverage of the first two days of DAC, see my posts DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley's Troublemakers, and DAC Tuesday: Thomas Dolby, the View from Wall Street, AI Lunch, Denali. Verifica...
- 6 Jun 2019
Breakfast Bytes: DAC Tuesday: Thomas Dolby, the View from Wall Street, AI Lunch, Denali

Paul McLellan

It was the second day of DAC yesterday. If you were here, you probably saw some of these main events. If not, then read on. I'll tell you what you missed. Thomas Dolby The keynote was Thomas Dolby, probably most famous for his single "She Blinded Me ...
- 5 Jun 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM) – Part 2

References4U

In this week’s Whiteboard Wednesdays video, Amol Borkar continues his discussion on SLAM including the benefits and weaknesses of different implementations and how the Vision Q7 DSP gives you the best performance, power, and capability of handling heavy compute workloads. Must watch!

www.youtube.com/watch
- 4 Jun 2019
System, PCB, & Package Design : IC Packagers: The (Copper) Pillars of Modern Design

Tyler

Wire bonding has been around forever. Flip-chip mounting? That’s been around for a long time as well. Every new generation of packages brings with it new technologies, challenges, and options. Copper pillars have been around for a fair time as ...
- 4 Jun 2019
System, PCB, & Package Design : BoardSurfers: Easier Design Work Through Colors, Patterns, and Visibility

Tyler

PCB and IC Package substrates these days are complex. Multiple layers, hundreds to thousands of components and pins, degassed and cross-hatched shapes, routing, and everything in between can make the visual depiction of your layout imposing, to put it mildly.

How, then, do you reclaim control? Focus on exactly what you need to see and when you need to see it? Are there ways to simplify determining whether the via you…
- 4 Jun 2019
Breakfast Bytes: DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley's Troublemakers

Paul McLellan

The Design Automation Conference is in Las Vegas this year. If you are here and want my recommendations, then see my post Top 10 Reasons to Go to DAC. If you are not here, and want to know some of what you missed, then this post covers a lot of what ...
- 4 Jun 2019
Academic Network: How to Show You’re a Verification Engineer?

Anton Klotz

There is always a need for verification engineers in the microelectronics industry. The costs of verification have long ago surpassed the costs of implementation, but still the focus in academia is on implementation and not too many universities offe...
- 3 Jun 2019
System, PCB, & Package Design : IC Packagers: Dealing with Large Forms in Low Resolution Screens

Monika

Our packages and boards are becoming complex and so are the design tasks we perform and the tools that we use. Although ease of use is the mantra for all our UIs, sometimes a form ends up having too many elements to address the ever-increasing requir...
- 3 Jun 2019
Digital Design: Need Help with Liberate Commands and Parameters?

Jommy

Alexa, what is square root of 12547858?

Within some nanoseconds, Alexa gives you the answer to it. That's how convenient technology has made things for us! How cool would it be if Alexa could get some help with the usage of parameters or commands while scripting?

Well, we don't have Alexa to your rescue yet, but do have a cool help functionality that could save you time and effort of pulling out a reference manual…
- 3 Jun 2019
Breakfast Bytes: Spectre X: Same Accuracy, New Speed

Paul McLellan

This morning at DAC, Cadence announced the Spectre X Simulator, the latest version of its circuit simulation product. The short value proposition is up to 10X speed improvement, up to 5X capacity improvement, the same golden accuracy. So the same res...
- 3 Jun 2019
Breakfast Bytes: Sunday Brunch Video for 2nd June 2019

Paul McLellan

https://youtu.be/T2VZUEW1ucc Made at Protium Hardware Lab (camera Sean) Monday: Memorial Day Tuesday: Protium X1: FPGA Prototyping for the Enterprise Wednesday: Verific, 20 Years Terrific Thursday: Embedded Vision: Seeing Round Corners, and...
- 2 Jun 2019
PCB、IC封装：设计与仿真分析: SI工程师如何分析多千兆位串行链路、内存及接口

Sigrity

作者：Ken Willis 早在2007年，Cadence推动了对IBIS标准的扩展，即算法模型接口（AMI），可以模拟多千兆位串行链路接口。这与通道（与传统电路相对）仿真密切相关，可以模拟大量位比特流量仿真。当时的数据速率通常在2.5到5Gbps的范围内——即现在DDR4和DDR5的速率范围。有几件事情推动了对串行链路中通道仿真和AMI的最初需求。一个是在特定误码率（BER）下分析眼图与眼图模板（即波形禁止区域）的要求。根据经验模拟确定误码率是不切实际的（模拟1e16...
- 31 May 2019
Life at Cadence: Appreciating Our Employees

Mihaylov

Recognizing the Outstanding Effort that Makes Cadence Successful Cadence hires the best and brightest in our industry to help us elevate the team and solve technology’s toughest challenges for our customers. Our employees make a global impact a...
- 31 May 2019
Breakfast Bytes: ESD Alliance CEO Outlook: The Leading Edge, Chiplets, Design Costs, Security, and More

Paul McLellan

The ESD Alliance (and, before that, its forerunner EDAC) runs a CEO Outlook panel one evening every spring. Originally, it was focused on the CEOs of the big EDA companies giving an outlook, but since one of them was always in its quiet period, and t...
- 31 May 2019
Verification: Got IP Security Questions? This Luncheon at DAC Has Answers

XTeam

If you’ve got security on the mind—and in this day and age, who doesn’t?—and you’re planning to attend DAC, be sure to stop by the Accellera-sponsored Luncheon Focusing on IP Security Assurance Issues Led by Panel of Industry Experts. There, you’ll hear a short update on what Accellera’s been up to by Accellera Chair Lu Dai, and then the experts will jump right into a panel discussion covering all sorts of IP security…
- 30 May 2019
Breakfast Bytes: Embedded Vision: Seeing Round Corners, and Reasoning on Microcontrollers

Paul McLellan

May is a month that seems to have many things associated with it. "Sell in May and go away," people who work in the financial sector will tell you. Or "I thought that spring must last forevermore; For I was young and loved, and it was ...
- 30 May 2019
Verification: DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety, Security and More

fschirrmeister

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...
- 29 May 2019
Analog/Custom Design: Spectre Tech Tips: Spectre APS Save Overview - Part 1

Stefan Wuensche

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Saving node voltages, element, and subcircuit port currents and power is an essential part when simulating your designs. Over the years, incremental additions to the Spectre waveform writing functionality have made it more complex. In SPECTRE17.1 ISR15, and SPECTRE18.1 ISR7 releases, we’ve consolidated…
- 29 May 2019
Breakfast Bytes: Verific, 20 Years Terrific

Paul McLellan

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL. Verific got started twenty years ago, Rob De...
- 29 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM) – Part 1

References4U

In this week’s Whiteboard Wednesdays video, Amol Borkar explains how SLAM works. From the creation of a map of an unknown environment and understanding the orientation of a camera in this space. Then he talks about the importance and the applications of SLAM. Finally, Amol talks about the building blocks of a SLAM flow. Must watch!

www.youtube.com/watch
- 28 May 2019
Verification: Thinci Finds Success with the Cadence Verification Suite

XTeam

On May 23rd, 2019, Cadence announced that Thinci has elected to use the complete Cadence Verification Suite to speed up the verification of their machine-learning and AI designs. Now, Thinci can access the new technologies available through the Cadence Verification Suite to shorten their product development time by months while improving verification coverage.

“We selected the Cadence Verification Suite because it enables…
- 28 May 2019
The India Circuit: Is The Gig Economy Is Here To Stay?

Madhavi Rao

While the term "gig economy" has been around a long time, it has gained traction in India only since around 2014 when Indian gig economy companies that hire a part-time workforce, such as Swiggy and Zomato (food delivery), Dunzo (delivery s...
- 28 May 2019

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