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Analog/Custom Design: Virtuoso Video Diary: Stimuli with Variable Sweeps Videos and Rapid Adoption Kit

Arja H

You're probably thinking, "wasn't there a recent blog on the new Stimuli Assignment form in ADE." Well yes, that's right, but we wanted to offer more functionality so from IC6.1.8 ISR4, we now have the ability to preview stimuli waveforms using swept variables. This will be really useful when defining your stimuli. There are a couple of other small usability changes too.
- 9 Aug 2019
Breakfast Bytes: AImotive: Shifting Gear in Automotive

Paul McLellan

At the recent Cadence Automotive Design Summit, Laszlo Kishonti, CEO of AImotive, presented From Walled Gardens to Collaboration: Shift in the Automated Driving Industry. AImotive is based in Budapest, and when introducing him, Cadence's Robert S...
- 9 Aug 2019
Breakfast Bytes: Mary Meeker: Security, Gigs, Healthcare, China

Paul McLellan

This is the third (of three) posts about Mary Meeker's 2019 report on Internet Trends. The first was on Monday. The second was yesterday. If you don't know who Mary Meeker is or what this report is, then start at the beginning....
- 8 Aug 2019
Breakfast Bytes: Mary Meeker: Fulfillment, News, and Money

Paul McLellan

This is the second post (of three) about Mary Meeker's 2019 report on Internet Trends. The first was yesterday. You should read that post first since this one simply picks up where that one left off. If you have no idea who Mary Meeker is, then y...
- 7 Aug 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Inductance Extraction for Digital Designs

References4U

In this week’s Whiteboard Wednesdays, Cadence expert Varun Raj Garapati explains how designers can address inductance effects on clocks, especially on digital SoCs. Using Quantus Extraction Solution for FinFET designs, designers can overcome reliability issues stemming from Inductance effects. To learn more visit https://www.cadence.com/go/quantus-extraction

www.youtube.com/watch
- 6 Aug 2019
System, PCB, & Package Design : IC Packagers: Six Steps of IC Packaging

mrigashira

Do you want to create an IC Package and are on the lookout for a tool that suits you? Or, you might already be using APD or SiP Layout but want to know their full potential. We will talk about six broad steps of IC Packaging and how APD and SiP Layout make the steps efficient and easy for you.
- 6 Aug 2019
System, PCB, & Package Design : BoardSurfers - Aerials and Bails: How to Rename Reference Designators Using Batch Command

Monika

Components on a board are often placed per their functional group and hence their reference designators are all jumbled up. It is a common practice to rename reference designators before sending out the design data to manufacturers. Reference designator...
- 6 Aug 2019
Breakfast Bytes: Mary Meeker: How Much Is the Internet Growing?

Paul McLellan

Every year Mary Meeker produces a big presentation on Internet Trends. And when I say big, I mean it. This year the presentation has 334 slides. In previous years, going back to 1995, Mary was a general partner at Kleiner Perkins, but she is now...
- 6 Aug 2019
Breakfast Bytes: Automotive Industry Basics

Paul McLellan

A couple of weeks ago Cadence held its second Automotive Design Summit here on the Cadence campus in San Jose. I will cover some of what was said over the next week or two, but I thought it might be good to do a recap on the basics of the automotive ...
- 5 Aug 2019
Breakfast Bytes: Sunday Brunch Video for 4th August 2019

Paul McLellan

https://youtu.be/5b0hczb-5FI Made at building 11 (camera Sean) Monday: Ludwigsburg: It's All About Return-on-Investment Tuesday: 5G in US vs Rest-of-World Wednesday: IEEE Unified Power Models Thursday: CHIPs: Interns around the World Friday:...
- 4 Aug 2019
Breakfast Bytes: My Boris Johnson Story

Paul McLellan

Boris Johnson is the new Prime Minister of Britain. Unlike most people who rise in politics, he has not been a career politician. Sure, he was Mayor of London from 2008 to 2016, beating the shoo-in Labor candidate and winning re-election to a se...
- 2 Aug 2019
Computational Fluid Dynamics: CREMHyG Analyzes Transient Flow in a Multi-Piston Pump Design

Veena Parthan

Author: Claude Rebattet, Head of CREMHyG laboratory, University of Grenoble Alpes, France The Grenoble Hydraulic Machinery Research and Testing Centre (CREMHyG) is a Grenoble Institute of Technology (Grenoble INP) laboratory. The turbomachinery te...
- 2 Aug 2019
PCB、IC封装：设计与仿真分析: Cadence Clarity为系统分析和设计提供前所未有的性能及容量

SDA China

本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“Bringing Clarity to System Analysis”。 space 今年4月在Cadence用户大会——CDNLive硅谷站，Cadence公司CEO陈立武（Lip-Bu Tan）宣布了发布Cadence® Clarity 3D Solver。这是Cadence公司系统级分析策略下推出的第一款产品，突破性的电磁场（...
- 1 Aug 2019
System, PCB, & Package Design : 3D EM Simulation Is Necessary

Sigrity

Accurate 3D EM simulation is increasingly necessary as data rates increase. For example, last year Cadence announced IP for 112G long-reach SerDes. The IP lives on a 7nm chip, which is a reasonably well-controlled environment. But think what the sig...
- 1 Aug 2019
Analog/Custom Design: Virtuosity: Automated Device Placement and Routing - Identifying Device Groups and Topologies

Sravasti

This blog highlights the importance of identifying device groups and topologies in the fully automated device-level placement and routing flow in Virtuoso.
- 1 Aug 2019
Breakfast Bytes: CHIPs: Interns Around the World

Paul McLellan

Cadence has an intern program that goes under the name CHIPs, for college hires and internship programs. I gave some background on it last year in my post CHIPs in the Cadence Cafeteria, and the year before in CHIP: College Hire and Internship P...
- 1 Aug 2019
System, PCB, & Package Design : IC Packagers: Multi-Wire Bonding with Ease Using Cadence IC Packaging Tools

Tyler

When wire bonding, the most common situation remains a single wire from pin to finger. There may be die to die connections as you step down from one die to the next in a stacked die situation (sometimes called a stitch bond, where the wire is tacked ...
- 31 Jul 2019
System, PCB, & Package Design : BoardSurfers: Capturing Design Intent for Automatic Routing in PCB Editor

mrigashira

Imagine you are designing a complex board with thousands of interconnects and all the usual complexities inherent in a dense design that is also highly constrained. Well, it's easy, the 'imagine' part; and you don't even have to try like John Lennon had crooned in his Imagine song, because most probably you are actually designing one right now that is dominated by bussed interconnect. And most probably…
- 31 Jul 2019
Breakfast Bytes: IEEE Unified Power Models

Paul McLellan

Today the IEEE announced the release of IEEE 2416-2019, a standard for unified power models. Last week, I talked to Jerry Frenkil of Si2, the Silicon Integration Initiative, to get the details. As it happens, Jerry joined VLSI Technology a couple of ...
- 31 Jul 2019
Whiteboard Wednesdays: Whiteboard Wednesdays – xSPI Standard Explained

References4U

In this week’s Whiteboard Wednesdays video, Jacek Duda explains the xSPI standard in detail, its uses, and benefits. The xSPI spec is the first to become an official JEDEC standard.

https://youtu.be/6Cr7WuhyMZc
- 30 Jul 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR5 and ICADVM18.1 ISR5 Now Available

Virtuoso Release Team

The IC6.1.8 ISR5 and ICADVM18.1 ISR5 production releases are now available for download.
- 30 Jul 2019
Analog/Custom Design: Spectre Tech Tips: Spectre Local Options

Stefan Wuensche

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Years back, we introduced the Multi-Technology Simulation (MTS) solution that allows you to simulate multiple chips in a single Spectre run, with each chip using its own device models, temperature definitions, and technology scaling setups. In the MMSIM 15. 1 (October 2015) release, MTS was made default…
- 30 Jul 2019
Breakfast Bytes: 5G in US vs Rest-of-World

Paul McLellan

While I was in Germany for the Automobil Elektronik Kongress, the results of the 5G auctions were just announced. Four companies paid €6.5B for spectrum. These were in the 2GHz and 3.5GHz bands. A few weeks earlier, the US Federal Communications...
- 30 Jul 2019
定制IC芯片设计 : Virtuoso视频日记: 比较多个测试和共享设置

Yuan Li

今天的博客重点介绍了现在ADE Assembler中提供的新Multi-Test Editor的功能。通过这个博客，我们已经结束了迷你博客系列，其中涵盖了Virtuoso®ADE Assembler, Virtuoso®ADE Explorer, Virtuoso®ADE Verifier和Virtuoso® Visualization and Analysis刚刚发布的有趣的功能。我们希望您发现这些博客很有用。点这里看我们在本系列中介绍的...
- 30 Jul 2019
Verification: Tales from DAC: Altair's HERO Is Your Hero

XTeam

Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out…
- 29 Jul 2019

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