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Whiteboard Wednesdays: Whiteboard Wednesdays - Passport Partners Program Expands Customer Cloud Deployment Options

References4U

In this week's Whiteboard Wednesdays video, Craig Johnson explains the purpose of the Cloud Passport Partners Program and how customers can now connect with authorized and knowledgeable service providers to tackle complex cloud deployment projects.www.youtube.com/watch
- 18 Jun 2019
Breakfast Bytes: DAC: The View from Wall Street

Paul McLellan

Jay Vleeschhouwer did his annual...well, he did it last year, too...View from Wall Street in the DAC Pavilion. I've known Jay for years since I spent a couple of years being the person in Cadence who was house-trained on what I could and could no...
- 18 Jun 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR4 and ICADVM18.1 ISR4 Now Available

Virtuoso Release Team

The IC6.1.8 ISR4 and ICADVM18.1 ISR4 production releases are now available for download.
- 17 Jun 2019
Breakfast Bytes: Designing a Wi-Fi HaLow Baseband in Less than Six Months

Paul McLellan

At CDNLive EMEA last month, Stefan Stanic of Methods2Business (M2B) presented The Challenge of Designing a First-TIme-Right Wi-Fi HaLow Baseband in Less than Six Months. WI-FI HaLow is a standard for superior IoT connectivity. Links can be up to 1km,...
- 17 Jun 2019
System, PCB, & Package Design : DATA Pulse: Know How to Effectively Manage Part Obsolescence (Part 1 of 2)

Auromala

This is the first of a two-part blog post on managing part obsolescence using Allegro^® EDM applications.

In the midst of a periodic bout of decluttering the house, my niece stumbled across some cassettes and looked at them like they were from some prehistoric age. How could I convey the importance of the audio cassette to my niece? She's used to iTunes, YouTube, Spotify, and goodness knows what else. I remember cassettes…
- 16 Jun 2019
Breakfast Bytes: Sunday Brunch Video for 16th June 2019

Paul McLellan

https://youtu.be/CaIc3qOakxs Made at building 9 elevator (camera Sean) Monday: Cadence Cloud Passport Partner Program Tuesday: Making Trouble in Las Vegas Wednesday: Paris Air Show Thursday: Ericsson Using Virtual Platforms for Dynamic Analysis ...
- 16 Jun 2019
PCB、IC封装：设计与仿真分析: 刚柔板装配与多板系统装配有何不同？

TeamAllegro

通常我们考虑多层电路板PCB设计时，往往会想到服务器环境中的电路板机架或游戏平台组合。但是如果我们的典型刚性电路板并不适合多层电路板使用的实体机壳怎么办？我们会愿意付额外的价格来使用柔性电路板吗？如果我们可以将这两者的优点兼而有之呢？本文中，我们将介绍刚柔组合的优点、性质以及如何更好地满足多层电路板的PCB设计需求。什么是刚柔结合的PCB? 在标准多层电路板PCB设计中，我们采用电路板概念，将不同功能电路划分到较小的电路板上，并采用各种互连线路将系统放进一个外壳内。这种标准方法的问题在于...
- 14 Jun 2019
Learning and Support: Single-Stop Learning Resource for JasperGold Formal Verification Platform

SumeetAggarwal

While Our next-generation cloud-ready JasperGold® Formal Verification Platform features machine learning technology and core formal technology enhancements across all JasperGold apps, and provides industry-leading performance, capacity, usability...
- 14 Jun 2019
Breakfast Bytes: Cell-Aware Test: Research Cooperation Between Cadence, imec, and TU Eindhoven...Now Shipping in Modus DFT Software Solution

Paul McLellan

At CDNLive EMEA, Zhan Gao presented her results on cell-aware test. This is the paper she presented at the Latin American Test Symposium (LATS) in Santiago, Chile in March and won the Best Paper award there (see Anton's post on the Academic Network b...
- 14 Jun 2019
Breakfast Bytes: Ericsson Using Virtual Platforms for Dynamic Analysis

Paul McLellan

At CDNLive EMEA last month, Ola Dahl of Ericsson presented Dynamic Software Analysis in Virtual Platforms. He described his job as "I work in the 5G network business doing basestations and radios." They have a virtual platform for one of th...
- 13 Jun 2019
Academic Network: Europractice and Cadence – A Long Fruitful Partnership

Anton Klotz

Those who have studied microelectronics in Europe since 1989 have certainly heard about Europractice and have probably used EDA technologies provided by them. Though most refer to Europractice as an organization, it is actually an EU-funded project, ...
- 12 Jun 2019
Verification: Specman: Python Is here!

teamspecman

Do you know from where Python technology gets its name? It is not from the snake, it is named after the Monty Python comedy group. And indeed, one of the main guidelines behind it is to be fun to use (check out the Zen of Python). Therefore, Python is intuitive, readable, and easy to learn - all of these make it not only fun to use but also highly productive. Does this sound familiar? If you are an e user, it should. Apparently…
- 12 Jun 2019
Breakfast Bytes: Paris Air Show

Paul McLellan

Next week it is the Paris Air Show, the biggest trade show in aerospace and defense. Cadence will be attending for the first time. The show is held at Le Bourget Airport, which you've probably never heard of. Although it was Paris's first air...
- 12 Jun 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Cadence Cloud - Fast, Painless, Proven Solutions for Cloud-Based Design

References4U

In this week's Whiteboard Wednesdays video, Tom Hackett continues his discussion of the unique needs of different types of companies and introduces the specific Cadence® Cloud solutions designed to meet those needs.

https://youtu.be/iTLy4sYQp1Q
- 11 Jun 2019
System, PCB, & Package Design : IC Packagers: A Classic Revisited - Ball Map Spreadsheets

Tyler

Interfaces to the major spreadsheet commands from OpenOffice, Microsoft, Google, and others are becoming more common in EDA, Cadence® SiP has had a great interface since early in the 16.6 release. You, our users, continue to find creative new use...
- 11 Jun 2019
System, PCB, & Package Design : BoardSurfers: Text Labels and Film Views Help Intelligent Designers

Tyler

Last time, I talked about color and visibility as it relates to simplifying your design canvas display to make your work easier. Today, we take the next step forward: using your artwork films to drive what you see on screen, as well as dynamic text labels to help you find objects. We’ll close out with a reminder of how to recycle the time you’ve spent setting up one design across all your designs.
Artwork…
- 11 Jun 2019
Breakfast Bytes: Making Trouble in Las Vegas

Paul McLellan

For years John Cooley has organized what is called the Cooley's DAC Troublemaker Panel. This year, the participants (troublemakers?) were: Naveed Sherwani, CEO of SiFive (a RISC-V implementation company) Joe Costello of Montana (creati...
- 11 Jun 2019
Analog/Custom Design: Virtuosity: Device-Level Routing for Advanced Nodes - Using Finish Trunk

Parula

The first blog of the series talks about features that are not new but capabilities that are ground-breaking and can support your device-level routing requirements for advanced nodes with the use of the Finish Trunk command.
- 10 Jun 2019
Learning and Support: Single-Stop Learning Resource for Cadence Low Power Simulation

SumeetAggarwal

Since 2006, low power design has evolved from simple shut off and isolation to very advanced design techniques. This evolution is still in full force. The CPF language was introduced in 2005, and the UPF language was introduced in 2006. Cadence suppo...
- 10 Jun 2019
Breakfast Bytes: Cadence Cloud Passport Partner Program

Paul McLellan

Last year at DAC, Cadence announced Cadence Cloud (see my post Cadence Cloud from that day for details). Since then we have announced CloudBurst (see my post CloudBurst: The Best of Both Worlds for those details), and various other foundry-based...
- 10 Jun 2019
Breakfast Bytes: Sunday Brunch Video for 9th June 2019

Paul McLellan

https://youtu.be/T8nSP-oElJM Made at Design Automation Conference (camera Sean) Monday: Spectre X: Same Accuracy, New Speed Tuesday: DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley's Troublemakers Wed...
- 9 Jun 2019
SoC and IP: SemiEngineering Article: Why IP Quality Is So Difficult to Determine

TomWong

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor.

So, how do you measure IP quality and why it is so complicated?

The answer depends on who is asking. Most of the time, the definition of IP quality depends…
- 7 Jun 2019
PCB、IC封装：设计与仿真分析: 线下专家培训第二站：PCB高效设计入门到进阶——第一期之设计环境准备

SDA China

前言大家好，我是Principal Customer Engagement Engineer郑凤仙，从事PCB设计行业十六年，先后受聘于Mitac、华为两家企业。熟悉PCB全流程设计，拥有丰富的PCB设计经验：在PCB设计工作中，做到了“零”设计事故。设计产品包括电脑主板、服务器、路由器等，擅长于PCB精细化设计及质量管控。 PCB设计工作需要具备很强的沟通能力，需要熟悉电路设计、工艺流程、结构设计等领域的基础知识，是一项综合性极高的工作。这几年的工作留给我的感受一直是...
- 7 Jun 2019
Academic Network: Carnegie Mellon University – Real World Engineering Program

Anton Klotz

Cadence San Jose was happy to host a group of undergraduate students from Carnegie Mellon University. Through the Real World Engineering program, students from CMU get the opportunity to visit different companies in Silicon Valley, Pittsbur...
- 7 Jun 2019
Analog/Custom Design: Virtuoso Video Diary: Can I Put Sticky Notes on Nets When Resolving EM Violations?

NamrataM

Do you know the Virtuoso Electrically Aware Design flow provides a sticky notes-kind of feature called point-to-point info balloons. These info balloons provide critical information that you would find handy while working with critical nets to resolve EM violations. Read more...
- 7 Jun 2019

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