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System, PCB, & Package Design : BoardSurfers: PCB Electronics - Six Things to Do Before You Actually Place Components on a PCB

mrigashira

It's a PCB you are designing. Where do you start? What can you do to make your process more productive and efficient? Are you feeling at lost? Worry not. We will talk about the six things you do before you start placing components on the board, and, of course, if you use PCB Editor, there is the Design Workflow guide to ease the board design process for you.
- 20 Aug 2019
System, PCB, & Package Design : IC Packagers: Choosing the Right Netlist to Match Your Needs

Tyler

Netlists. Everyone needs them! But what you are using your netlist for can have a significant influence on just what KIND of netlist you want. Fortunately, the Cadence SiP tools offer formats for just about every situation you might run into, from in...
- 20 Aug 2019
Breakfast Bytes: CDNLive India 2019 Preview

Paul McLellan

CDNLive India is coming up next week. It will be August 28 and 29 at the Radisson Blu Hotel, Marathahalli in Bengaluru (fka Bangalore). I will be attending as usual so you can expect some Breakfast Bytes posts over the following couple of weeks....
- 20 Aug 2019
Breakfast Bytes: HOT CHIPS 2019

Paul McLellan

This week is HOT CHIPS. It has moved from the Flint Center at De Anza College, where it has been for years, and is now in the Stanford Memorial Auditorium, which I don't believe I've ever been in before. Last week was also HOT INTERCONNECTS, held at ...
- 19 Aug 2019
定制IC芯片设计 : Virtuosity: ADE What’s New 中文版上线!

Rashmi G

您知道当您有感情需要抒发时，脱口而出便是母语。想知道为什么吗？这是我们与生俱来的本能。我们一般使用英语作为商业通用语言，但是我敢打赌，如果换成是自己的母语，大家会感到更开心舒适？ “如果你以一种外语和一个人交流，你的话只是进入他的大脑；如果你以他的母语和他交流，你的话能深入他的内心。” &...
- 19 Aug 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Here's All You Must Know to Create a TILP

deeptig

Did you get a chance to look at the outstanding posts about Technology Independent Layout Pcell (TILP) in the Virtuoso Meets Maxwell series, TILP! What’s a TILP? and Export the Die? What Am I Exporting? To Where?? I am sure it would have been nearly impossible sometime ago to imagine a feature like this being offered in Virtuoso. Now, the Virtuoso RF Solution has brought the revolution by enabling you to create modules…
- 19 Aug 2019
System, PCB, & Package Design : DATA Pulse: Playing Favorites with Parts—Influencing Design Part Selection with a Preferred Parts List

Auromala

Life is full of decisions - what college major to opt for, which career path to follow, whether to move cities for a job or stay put, whether to switch career paths midstream for a more fulfilling life. You know what I mean.

As a librarian, your professional life is as full of choices and decisions to be made. OK, so maybe they're not as life changing as the ones I've just listed, but they're important. However, it's…
- 18 Aug 2019
Breakfast Bytes: Sunday Brunch Video for 18th August 2019

Paul McLellan

https://youtu.be/xGAnEry49nw Made on my balcony (camera Carey Guo) Monday: Arm on Autonomous Automotive Tuesday: Black Hat: Phishing on Gmail Wednesday: CDNLive Taiwan Thursday: Black Hat: Glitching Microcontrollers Friday: Maglev Trains www.breakfas...
- 18 Aug 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之二 | 千兆位串行链路接口的SI方法

Sigrity

作者：Ken Willis 上一篇：通过“自上而下”的方法将SI推向上游假设我们正在致力于PCI Express Gen 4串行链路的研发，数据的传输速率为16Gbps。再假设我们能够获得供应商提供的AC耦合电容、封装和连接器的模型，以及来自SerDes接收端的IBIS-AMI模型。接下来还需要PCB的走线和过孔模型，以及发射端的IBIS-AMI模型。假设供应商暂时无法提供这些数据，那就让我们先来解决PCB架构的问题吧。 PCB互连的预布局建模 PCB走线的建模可以从获...
- 16 Aug 2019
Breakfast Bytes: Maglev Trains

Paul McLellan

Earlier this week I was in Shanghai for CDNLive China. More about what was said there next week. Today's post is about getting to the hotel where CDNLive was held from the airport. Most people just take a taxi, but I like to try and use the local tr...
- 16 Aug 2019
Analog/Custom Design: Virtuosity: Automated Device Placement and Routing - Grid Generation

Sravasti

This blog, the third one in the Automated Device-Level Placement and Routing series, highlights the importance of following a gridded methodology for placement and routing. You'll see how the automated device-level layout flow lets you derive WSPs and row regions automatically, based on the device footprint, layers, and DRCs, with minimal user input.
- 15 Aug 2019
Breakfast Bytes: Black Hat: Glitching Microcontrollers

Paul McLellan

As a paid-up member of the semiconductor community, the most interesting presentation I saw at Black Hat was about glitching microcontrollers. One way that chips are vulnerable to security issues is that all our chip knowledge tells us that things ar...
- 15 Aug 2019
Breakfast Bytes: CDNLive Taiwan 2019

Paul McLellan

I haven't been to Taiwan since the last time I worked for Cadence in the early 2000s. At that time, I was running Custom IC, which also included physical verification—we were structured a bit differently back then. However, one reason behind th...
- 14 Aug 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - An Introduction to Palladium Cloud

References4U

In this week's Whiteboard Wednesdays video, Bennet Le provides an overview of the Cadence® Palladium® Cloud Solution and explains how virtually every company developing SoC designs can now take advantage of the extensive verification provided by the Palladium platform.

https://youtu.be/xLL6ynSm51o
- 13 Aug 2019
System, PCB, & Package Design : IC Packagers: Grouping Items with Symbol Instances

Tyler

Whether you’re adding lines, text, shapes, routing elements, or any other feature to the design, most elements assume that you are placing them at the design level. If they are part of the symbol, they would be part of the library object. Is there a quick and convenient way to take the additional elements and assign them to the placed symbols in your design so that everything stays together in easy to manipulate pieces…
- 13 Aug 2019
System, PCB, & Package Design : BoardSurfers: Five Ways to View Your Design in 3D Canvas

Monika

Five simple yet effective ways to increase efficiency by selecting the right objects you want to model, say, all the pins or a subset of the pins in a design.
- 13 Aug 2019
Breakfast Bytes: Black Hat: Phishing on Gmail

Paul McLellan

A few weeks ago I wrote a post Passwords and Multi-Factor Authentication about the scale of attacks on cloud providers and other services. At the recent Black Hat Security Conference in Las Vegas, Google's research lead for security, Elie Bu...
- 13 Aug 2019
Breakfast Bytes: Arm on Autonomous Automotive

Paul McLellan

Let me start this post with a brief history of autonomous driving. Most people date the start of the autonomous driving era to 2004, with the Grand Challenge in the Mojave Desert over a 150-mile course. That turned out to be 142 miles longer tha...
- 12 Aug 2019
Breakfast Bytes: Sunday Brunch Video for 11th August 2019

Paul McLellan

https://youtu.be/ZXa5ZZzAWXs Made at Cadence campus (camera Sean) Monday: Automotive Industry Basics Tuesday: Mary Meeker: How Much Is the Internet Growing? Wednesday: Mary Meeker: Fulfillment, News, and Money Thursday: Mary Meeker: Security, Gi...
- 11 Aug 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之一 | 多千兆串行接口的信号完整性方法

Sigrity

作者：Ken Willis 随着电子行业技术的发展，特别是在传输接口方面，从PCI到PCI Express、从ATA到SATA、从并行ADC接口到JESD204、从RIO到Serial RIO等等，无一都证明了传统并行接口的速度已经达到瓶颈，取而代之的是速度更快的串行接口，于是原本用于光纤通信的SerDes 技术成为了高速串行接口的主流。串行接口主要应用了差分信号传输技术，具有功耗低、抗干扰强，速度快的特点，诸如PCI Express®（PCIe®）Gen4等串行链路接口的数据传...
- 9 Aug 2019
Analog/Custom Design: Virtuoso Video Diary: Stimuli with Variable Sweeps Videos and Rapid Adoption Kit

Arja H

You're probably thinking, "wasn't there a recent blog on the new Stimuli Assignment form in ADE." Well yes, that's right, but we wanted to offer more functionality so from IC6.1.8 ISR4, we now have the ability to preview stimuli waveforms using swept variables. This will be really useful when defining your stimuli. There are a couple of other small usability changes too.
- 9 Aug 2019
Breakfast Bytes: AImotive: Shifting Gear in Automotive

Paul McLellan

At the recent Cadence Automotive Design Summit, Laszlo Kishonti, CEO of AImotive, presented From Walled Gardens to Collaboration: Shift in the Automated Driving Industry. AImotive is based in Budapest, and when introducing him, Cadence's Robert S...
- 9 Aug 2019
Breakfast Bytes: Mary Meeker: Security, Gigs, Healthcare, China

Paul McLellan

This is the third (of three) posts about Mary Meeker's 2019 report on Internet Trends. The first was on Monday. The second was yesterday. If you don't know who Mary Meeker is or what this report is, then start at the beginning....
- 8 Aug 2019
Breakfast Bytes: Mary Meeker: Fulfillment, News, and Money

Paul McLellan

This is the second post (of three) about Mary Meeker's 2019 report on Internet Trends. The first was yesterday. You should read that post first since this one simply picks up where that one left off. If you have no idea who Mary Meeker is, then y...
- 7 Aug 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Inductance Extraction for Digital Designs

References4U

In this week’s Whiteboard Wednesdays, Cadence expert Varun Raj Garapati explains how designers can address inductance effects on clocks, especially on digital SoCs. Using Quantus Extraction Solution for FinFET designs, designers can overcome reliability issues stemming from Inductance effects. To learn more visit https://www.cadence.com/go/quantus-extraction

www.youtube.com/watch
- 6 Aug 2019

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