Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Breakfast Bytes: Protium X1: FPGA Prototyping for the Enterprise

Paul McLellan

Today Cadence announced the new Protium X1 Enterprise Prototyping Platform. The previous version, the Protium S1 Desktop Prototyping Platform, was the size of a small refrigerator and intended to be beside an engineer's desk. The Protium X1 platform,...
- 28 May 2019
System, PCB, & Package Design : IC Packagers: When Being Two-Sided is a Good Thing

Tyler

With each new generation, demand for smaller, faster, lighter, more efficient is at the top of the requirements list for most things. But, we cannot make things smaller forever. Instead, we need to look for more creative solutions. Where can we ...
- 28 May 2019
Breakfast Bytes: Sunday Brunch Video for 26th May 2019

Paul McLellan

https://youtu.be/mx1i55BxSTU Made at Cadence campus (camera Sean) Monday: Alberto and the Origins of the EDA Industry Tuesday: Samsung's 3nm GAA Process Wednesday: I/O Is Faster Than the CPU—What Now? Thursday: GOMAC: Software Is...
- 26 May 2019
System, PCB, & Package Design : BoardSurfers - Aerials and Bails: Minimum Screen Resolutions and Large Forms

Tyler

The Cadence® Allegro® backend layout tools are large, complex, highly-capable environments that provide you with a massive amount of functionality. Whether you are designing a rigid-flex PCB, a BGA package, an interposer, or something else entirely, they provide the features you need to accomplish the task.

However, with great functionality comes great… big forms, at times. Some of the largest forms in Allegro…
- 25 May 2019
PCB、IC封装：设计与仿真分析: 邀请函：2019 Cadence中国技术巡回研讨会

SDA China

诚邀您参加 “ 2019年度Cadence中国技术巡回研讨会”，会议将集聚Cadence的技术用户、开发者与Cadence资深技术专家，涵盖最完整的先进技术交流平台，从SoC设计、验证仿真到封装和板级设计的全流程的技术分享，您将有机会和开发Cadence工具的技术专家们面对面的直接沟通。 6月伊始，Cadence与您相约西安、成都、上海、深圳、北京！ space 会议为免费参加，座位有限，报名从速！会议咨询： event_cn@cadence.com 扫描下列二维码...
- 24 May 2019
Breakfast Bytes: Off-Topic: Syllepsis and Zeugma

Paul McLellan

It's Memorial Day in the US on Monday, and Cadence is off. So today is the day before a holiday. By tradition, I write about...whatever I feel like. So let's go with figures of speech. Even before I became a professional writer, I had a fasci...
- 24 May 2019
System, PCB, & Package Design : How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI

Sigrity

With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 di...
- 23 May 2019
Breakfast Bytes: GOMAC: Software Is Never Done

Paul McLellan

When I was at GOMAC in Albuquerque at the end of March, I ran into a couple of Cadence people and a couple of Green Hills people. Everyone left except one of the Green Hills guys, since he was staying in a different hotel. He turned out to be John Wa...
- 23 May 2019
Breakfast Bytes: I/O Is Faster than the CPU—What Now?

Paul McLellan

At his keynote at CDNLive Silicon Valley, Andy Bechtolsheim made a throwaway remark that 1600G Ethernet would be a problem since "the packet rate is just 333 picoseconds so that needs wide Ethernet ports" (see my post Andy Bechtolsheim...
- 22 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - The 4 Steps Necessary for an Effective Cloud-Based Design Strategy

References4U

In this week's Whiteboard Wednesdays video, Craig Johnson identifies the 4 steps to follow to create an effective strategy for moving electronic design work to the cloud. Skip one of these and your results could be disappointing.

https://youtu.be/rKoatyYa35E
- 21 May 2019
Analog/Custom Design: Virtuoso Video Diary: Comparing Multiple Tests and Sharing Settings

Yuan Li

Have you been in the situation where you want to change a particular simulation setting in several of your tests in Virtuoso ADE Assembler? This can be a tedious process as you have to figure out which tests have that setting and what it is set to, then you have to go in to each test in turn to change it. From IC6.1.8 ISR3/ICADVM18.1 ISR3, we have added a tool to do just that. You can compare all the simulator settings…
- 21 May 2019
System, PCB, & Package Design : IC Packagers: Expanding Your (Thermal) Repertoire

Tyler

The process of attaching a component to your package substrate involves many factors, including heat. What happens whenever heat is applied to something? Expansion, of course! How much your die expands during the assembly process will be influenced b...
- 21 May 2019
Breakfast Bytes: Samsung's 3nm GAA Process

Paul McLellan

At the recent Samsung Foundry Forum, HK Kang, the EVP of semiconductor R&D, took to the stage. He's in charge of advanced logic, DRAM, 3D NAND, mask. But that day he was just going to talk about Samsung's 3nm gate-all-around (GAA) technol...
- 21 May 2019
Breakfast Bytes: Alberto and the Origins of the EDA Industry

Paul McLellan

At the 2019 International Symposium of Physical Design, the conference honored Alberto Sangiovanni-Vincentelli with a lifetime achievement award. Alberto was one of the cofounders of SDA Systems, the forerunner of Cadence, so in some ways he's a foun...
- 20 May 2019
Breakfast Bytes: Sunday Brunch Video for 19th May 2019

Paul McLellan

https://youtu.be/cTEPUNpqcRg Made at Samsung HQ (camera Sean) Monday: Bob Smith on ESD Alliance, ES Design West...with Wine Tuesday: After Meltdown and Spectre Wednesday: Vision Q7 DSP: Real-Time Vision and AI at the Edge Thursday: Samsung ...
- 19 May 2019
PCB、IC封装：设计与仿真分析: 汽车以太网应用的SI分析技术

Sigrity

现今汽车中车载电子设备的爆炸式增长，正在迅速改变向汽车消费者圆满提供高性能、可靠功能所需的工具和方法。汽车印刷电路板（PCB）的设计传统上一直由几个简单的器件互连组成、使用2层PCB，主要考虑的是成本问题。但是随着先进驾驶员辅助系统（ADAS）的普及，现在汽车可以包含多达100个电子控制模块（ECU），通过多线缆电缆束与安装在汽车四周的传感器相连。为适应传感器、数字逻辑与ECU之间更高性能的传输，汽车中所用部件之间的信号传输也在发生变化。目前大多数汽车采用的设计标准是100BASE-T1网络...
- 17 May 2019
Academic Network: CDNLive EMEA 2019, Impressions from the Academic Track

Anton Klotz

CDNLive EMEA 2019 was held May 6-8 in Munich, Germany. Bayern Munich did not qualify for the Champions League this year, so we were completely undisturbed and could listen to presentations, visit the exhibition, explore new ideas on collaboration and...
- 17 May 2019
Breakfast Bytes: Top 10 Reasons to Go to DAC

Paul McLellan

The Design Automation Conference is coming up soon. It's in Las Vegas from June 2 to 6 in the Las Vegas Convention Center (LVCC). Rob Aitken I was putting together a post on what I thought were good reasons to attend, but I decided to c...
- 17 May 2019
System, PCB, & Package Design : IC Packagers: Create Daisy Chain Substrates in a Flash with Cadence SiP Layout

Tyler

How do you go about testing your IC or package substrate when it comes to physical endurance? For many of us, a daisy chain test package is a common option. With practical uses including extreme environmental and temperature testing scenarios, a dais...
- 16 May 2019
Analog/Custom Design: Virtuoso Video Diary: The Next Big Thing — ADE Verifier Teams Up with Cadence vManager

Rashmi G

Need to perform functional verification of a mixed-signal design? Using the connection between Verifier and vManager, analog and digital engineers get to work together with two different tools using the same data. A single view allows a project manager to look up all the results together and the engineers to sign off the project. You have fulfilled traceability and tracking of results for internationally acknowledged…
- 16 May 2019
Breakfast Bytes: Samsung Process Roadmaps

Paul McLellan

Recently, Samsung held the third Samsung Foundry Forum (SFF) at the Marriott in Santa Clara. They had so many attendees that they pretty much overflowed the biggest ballroom in the hotel and had to set up a temporary structure in the parking lot for ...
- 16 May 2019
SoC and IP: Designing for the Future - Managing the Impact of Moore's Law

TomWong

With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage improvements in process technology to get performance improvements for many years now. Let’s examine whether or not this assumption is still valid.

When we were at more mature technologies, such as 90nm to 65nm, there…
- 15 May 2019
Breakfast Bytes: Vision Q7 DSP: Real-Time Vision and AI at the Edge

Paul McLellan

At CDNLive EMEA, we announced the latest member of the Tensilica family at the press conference, although it was embargoed until this morning. This is the Tensilica Vision Q7 DSP. The earliest Vision cores were purely focused on image processing in t...
- 15 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Featuring the new Tensilica Vision Q7 DSP IP for Vision and AI

References4U

In this week’s Whiteboard Wednesdays video, Pulin Desai talks about the latest addition to the Vision DSP family, the Vision Q7 DSP. The Vision Q7 DSP offers up to 1.7X higher TOPS in the same area as Vision Q6 DSP. The Vision Q7 DSP provides 2X greater AI and floating-point performance compare to Tensilica Vision Q6 DSP. It is also optimized for simultaneous localization and mapping (SLAM) through instruction and architectural…
- 15 May 2019
Analog/Custom Design: Virtuosity: Did My Checks Pass or Did They Not Run?

AdityaMainkar

If you've ever tried to run the Checks/Asserts flow in Virtuoso ADE Assembler and Virtuoso ADE Explorer, you might have found it difficult to distinguish between “all checks passed” and “no checks were run”. In both the cases, the message “No violations” was displayed. Now, in IC6.1.8 ISR3 and ICADVM18.1 ISR3, you can differentiate when checks were not run or if they were ignored with syntax errors.
- 14 May 2019

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.