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Latest Blog Posts

  • Verification: Tales from DAC: Altair's HERO Is Your Hero

    XTeam
    XTeam

    Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out…

    • 29 Jul 2019
  • Breakfast Bytes: Ludwigsburg: It's All About Return-on-Investment

    Paul McLellan
    Paul McLellan
    I attended the Automobil Elektronik Kongress at Ludwigsburg outside Stuttgart. it was the 23rd year that it has run, and the third that I have attended. The atmosphere has been very different at all three. I summarized the changes affecting the autom...
    • 29 Jul 2019
  • Breakfast Bytes: Sunday Brunch Video for 28th July 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/-36euXtgU7Y Made at Cadence Summer of Love Party (camera Chad Yee) Monday: Passwords and Multi-Factor Authentication Tuesday: Virtuoso Meets Maxwell Wednesday: Computer Scientist Alan Turing to Be on British £50 Note Thurs...
    • 28 Jul 2019
  • PCB、IC封装:设计与仿真分析: 开放注册:2019 Cadence中国用户大会

    SDA China
    SDA China
    Cadence中国用户大会 CDNLive China 2019 上海浦东嘉里大酒店 - 2019年8月15日星期四 space 亲爱的用户朋友: 一年一度的Cadence全球用户大会CDNLive China 2019即将来到中国!2019年度的CDNLive China 将于8月15日在上海举办,会议将集聚Cadence的技术用户、开发者与业界专家,涵盖最完整的先进技术交流平台,从IP/SoC设计、验证仿真到封装和板级设计的全流程的技术分享, 以及针对汽车自动驾驶、智能感知、语音交互、机器...
    • 26 Jul 2019
  • System, PCB, & Package Design : BoardSurfers: Designing a Rigid-Flex Board Using PCB Editor

    mrigashira
    mrigashira

    BoardSurfers: Cadence Allegro BlogWhether you are designing the latest pace-maker or a LED strip, you have definitely pondered awhile about rigid PCBs and flex PCBs. You might have gone through a pile of literature, called up friends who have already done it (after all flex PCBs have been around for more than half a century now), and deliberated with your team to finally settle on a rigid-flex PCB. Well, what had started as a cutting-edge requirement to…

    • 26 Jul 2019
  • Breakfast Bytes: Digital Twins at the Paris Air Show

    Paul McLellan
    Paul McLellan
    The idea of a digital twin should be easy for anyone in aerospace to understand. After all, pilots learn to fly planes on simulators of various kinds, which are digital twins. There are two main types, the cheaper ones have the cockpit and graphics b...
    • 26 Jul 2019
  • Breakfast Bytes: Galileo Down for a Week

    Paul McLellan
    Paul McLellan
    You might never have heard of Galileo, the European Union's GNSS, or Global Navigation Satellite System. That's because your phone probably uses the US system known as GPS or Global Positioning System. There are actually four GNSSs: GPS (US),...
    • 25 Jul 2019
  • Honda Demonstrates a Major Breakthrough in Meshing Speed with AutoSeal and Hexpress

    Computational Fluid Dynamics: Honda Demonstrates a Major Breakthrough in Meshing Speed with AutoSeal and Hexpress

    AnneMarie CFD
    AnneMarie CFD
    Authors: Akio Takamura, Chief Engineer, Honda R&D, and Benoit Mallol, Head of Marine Products & Applications Group, Cadence It is common knowledge that 80% of the throughput time of a CFD simulation is spent on preparation and set-up. ...
    • 25 Jul 2019
  • 定制IC芯片设计 : Virtuoso 视频日记: 下一件大事 - ADE Verifier与Cadence vManager合作

    Rashmi G
    Rashmi G
    今天的博客重点介绍了ADE Verifier的最新增强功能。这个博客我们每周二和周四发布的迷你博客系列的一部分,以涵盖 Virtuoso®ADE Assembler , Virtuoso®ADE Explorer, Virtuoso®ADE Verifier和Virtuoso® Visualization and Analysis 的刚刚发布的功能。这个有趣的博客系列现在即将结束...... 现在只剩下最后一个博客!所以请继续关注。 在我们之前的文章中,我们...
    • 24 Jul 2019
  • Verification: Tales from DAC: Semiconductor Design in MY Cloud? It's More Likely Than You Think

    XTeam
    XTeam

    Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

    What people refer to as “the cloud…

    • 24 Jul 2019
  • Analog/Custom Design: Virtuosity: bindStrict or Not in Virtuoso in the Times of Chandrayaan 2

    Rishu Misri Jaggi
    Rishu Misri Jaggi
    Really, can Virtuoso bind strict? And what does that mean? Read along to find out...
    • 24 Jul 2019
  • Breakfast Bytes: Computer Scientist Alan Turing to Be on British £50 Note

    Paul McLellan
    Paul McLellan
    Last week the Bank of England announced that the new £50 note will have Alan Turing on it. The current note features James Watt and Matthew Bolton, the pioneers of the steam engine. It was determined early that the new note would continue to fe...
    • 24 Jul 2019
  • Whiteboard Wednesdays: Whiteboard Wednesdays – The Storage Combo PHY IP – Nirvana!

    References4U
    References4U

    In this week’s Whiteboard Wednesdays video, Jacek Duda describes three storage protocols and announces that you only need one PHY IP to support xSPI, ONFI 4.x and SD standards!

    https://youtu.be/cVi4FEpfpY4

    • 23 Jul 2019
  • Breakfast Bytes: Virtuoso Meets Maxwell

    Paul McLellan
    Paul McLellan
    When I was a postgraduate at Edinburgh University, my office was in the James Clerk Maxwell Building, the JCMB. Maxwell was most famous for Maxwell's Equations, which give the rules for how electrical and magnetic forces interact, and how electromagn...
    • 23 Jul 2019
  • System, PCB, & Package Design : IC Packagers: Correcting Die Orientations and Die Attachments

    Tyler
    Tyler
    When you add a die component to your SiP Layout design, you must identify both its default attachment type – wire bond or flip-chip – and its orientation – chip up or down. But, what happens if you get this wrong? The most common re...
    • 23 Jul 2019
  • 定制IC芯片设计 : Virtuosity: 我的 Checks 通过还是没有运行?

    AdityaMainkar
    AdityaMainkar
    今天的博客重点介绍 Checks/Asserts 结果显示和 Summary 表。 这个博客是我们每周发布两次 - 周二和周四 - 的迷你博客系列的一部分,以涵盖 Virtuoso®ADE Assembler,Virtuoso®ADE Explorer 和 Virtuoso® Visualization and Analysis中刚刚发布的功能。 请继续关注更多此类有趣的博客。 如果您曾尝试在 Virtuoso® ADE Assembler 和&...
    • 22 Jul 2019
  • Analog/Custom Design: Tales from DAC: MediaTek's Experience with Spectre X Simulator

    XTeam
    XTeam

    MediaTek recently gave the new Spectre X Simulator a try, and they talked about their experiences with it at DAC 2019 in a presentation given by YY Chen in the Cadence Theater.

    Spoiler alert: they loved it.

    MediaTek is the fourth largest fabless IC design company in the world, and they’re ranked #1 in the voice assistant device, android tablet, and network connectivity markets, among others. They, like so many others…

    • 22 Jul 2019
  • System, PCB, & Package Design : DATA Pulse: In Search of the Perfect Environment—Configuring Allegro EDM

    Auromala
    Auromala

      Ah, the office temperature – that eternal debate. As in many offices, ours has some people who feel that they're in the Sahara Desert, others who bundle up like they're in Antarctica, a few who just don't care about the temperature, and some who can't quite figure out if they're ever comfortable, like Goldilocks. There is however no 'perfect' temperature. So many variables impact the physical environment of the office…

    • 22 Jul 2019
  • Analog/Custom Design: Virtuoso Meets Maxwell: Export the Die? What Am I Exporting? To Where?

    kgjudd
    kgjudd
    Here I come back with another episode of TILP of the Virtuoso Meets Maxwell series! In my earlier post "TILP! What's A TILP?", I introduced the concept of Technology Independent Layout Pcell (TILP). Today we are going to create a TILP, which is used in the package design, from a die.
    • 22 Jul 2019
  • Breakfast Bytes: Passwords and Multi-Factor Authentication

    Paul McLellan
    Paul McLellan
    I recently came across an interesting piece written by Microsoft's Alex Weinert, Your Pa$$word doesn't matter. He is part of Microsoft's Security and Protection Team. As such he is involved in keeping Microsoft's Azure Cloud solu...
    • 22 Jul 2019
  • Breakfast Bytes: Sunday Brunch Video for 21st July 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/JHWXXezFMU8 Made at Krakow, Poland (camera Gary Bengier) Monday: Will American Scooters Follow Chinese Bikes? Tuesday: GLOBALFOUNDRIES After the Pivot Wednesday: Intelligent System Design for Automobiles of the Future Thursday: ...
    • 21 Jul 2019
  • Breakfast Bytes: The First Computer on the Moon

    Paul McLellan
    Paul McLellan
    I am sure you can't fail to have noticed that tomorrow is the 50th anniversary of the first landing on the moon. It has been everywhere for the last few weeks. I was a teenager. I remember watching the landing. In Britain, in the basement at my p...
    • 19 Jul 2019
  • PCB、IC封装:设计与仿真分析: 关于PCB安装孔所需了解的一切

    TeamAllegro
    TeamAllegro
    安装孔似乎很简单——只需将印刷电路板安装到外壳或表面上,选择一个适合电路板以及待安装表面的螺丝尺寸,然后根据此规格钻孔即可。 但与印刷电路板中其他设计一样,当增加高速信号并减小形状因子后,安装孔将变得复杂起来。突然间,每个导电层都能影响电磁干扰覆盖区域,包括安装孔。这时,我们就需要考虑公差,从而确保为电路板上所需的所有元件、过孔和走线留足间隙。 那么,除了目视要求,安装孔设计还应该注意哪些方面呢? 安装孔配置 安装孔通常可分为两类: 带有支撑特性:通常连接接地平面的电镀...
    • 18 Jul 2019
  • Analog/Custom Design: Virtuosity: Introducing Automated Device Placement and Routing in Virtuoso

    Sravasti
    Sravasti
    This blog provides an overview of the fully automated device-level placement and routing solution, which is available at advanced nodes.
    • 18 Jul 2019
  • Verification: Tales from DAC: Cadence, AI, and You

    XTeam
    XTeam

    Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore…

    • 18 Jul 2019
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