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Whiteboard Wednesdays: Whiteboard Wednesdays - Featuring the new Tensilica Vision Q7 DSP IP for Vision and AI

References4U

In this week’s Whiteboard Wednesdays video, Pulin Desai talks about the latest addition to the Vision DSP family, the Vision Q7 DSP. The Vision Q7 DSP offers up to 1.7X higher TOPS in the same area as Vision Q6 DSP. The Vision Q7 DSP provides 2X greater AI and floating-point performance compare to Tensilica Vision Q6 DSP. It is also optimized for simultaneous localization and mapping (SLAM) through instruction and architectural…
- 15 May 2019
Analog/Custom Design: Virtuosity: Did My Checks Pass or Did They Not Run?

AdityaMainkar

If you've ever tried to run the Checks/Asserts flow in Virtuoso ADE Assembler and Virtuoso ADE Explorer, you might have found it difficult to distinguish between “all checks passed” and “no checks were run”. In both the cases, the message “No violations” was displayed. Now, in IC6.1.8 ISR3 and ICADVM18.1 ISR3, you can differentiate when checks were not run or if they were ignored with syntax errors.
- 14 May 2019
Breakfast Bytes: After Meltdown and Spectre

Paul McLellan

At the recent Linley Spring Microprocessor Conference, the second day's keynote was by Jon Masters of Red Hat. He wears two hats (both of them red) since he is responsible both for their Arm product line and also their response to the Spectre and...
- 14 May 2019
Digital Design: LIBERATE 19.2 Base Release Now Available

LIBERATE Team

The LIBERATE 19.2 production release is now available for download at Cadence Downloads.

For information about supported platforms, compatibility with other Cadence tools, and details of key issues resolved in the LIBERATE 19.2 release, see the README.txt file.

At the time of publishing, the link above was functional. If you encounter any links that are now obsolete, visit https://downloads.cadence.com, click the LINUX…
- 13 May 2019
Breakfast Bytes: Bob Smith on ESD Alliance, ES Design West...with Wine

Paul McLellan

I talked to Bob Smith recently about what's coming up in the world of the ESD Alliance now that it is part of SEMI. One thing that Bob told me is that finally there are baby steps being taken outside of the US (Silicon Valley even) with a two-hou...
- 13 May 2019
Breakfast Bytes: Sunday Brunch Video for 12th May 2019

Paul McLellan

https://youtu.be/E61e34IbaRE Made at CDNLuve EMEA (camera Andrea Huse) Monday: Statistical Power...or Why You Shouldn't Be Allowed to Turn Right on Red Tuesday: JasperGold: the Next Generation Wednesday: How Do Out-of-Order Processors W...
- 12 May 2019
PCB、IC封装：设计与仿真分析: 通过人工神经网络探讨信号完整性的未来

Sigrity

想象一下，如果电脑或机器人可以完成所有枯燥乏味的工作，我们就能享受生活、做更多有意义的事。这些绝对是许多学术界、工业界研究人员的愿望。工程师的最终梦想是，按下一个“魔法按钮”，自动实现产品的设计、layout和优化，并满足性能参数和可制造性，这依然是科幻小说的情节，但现在各种实验设计（DOE）的运用使得技术已取得巨大的进步，特别是人工神经网络（ANN）。 space 正如我们所知，人工智能和神经网络的概念已经存在了几十年。直到近期，在2015年左右，相对“廉...
- 10 May 2019
Digital Design: HLS Optimizations You Can't Do By Hand

SeanDart

In my previous blog post, I talked about the Quality-of-Results (QoR) that are achievable using High-Level Synthesis tools like Stratus HLS and the fact that exploration of multiple RTLL architectures is often the feature that enables HLS users to beat hand-coded RTL flows in terms of QoR. That article raised the notion that "project schedule" is a critical factor when judging comparative QoR, and it often gets left out…
- 10 May 2019
Breakfast Bytes: 150th Anniversary of the Transcontinental Railroad

Paul McLellan

150 years ago, technology meant railroads, not semiconductors. I mean, precisely 150 years ago—today is the 150th anniversary of the completion of the transcontinental railroad from Oakland to Omaha, completed with a golden spike. I had a frien...
- 10 May 2019
System, PCB, & Package Design : Finally, A Certified and Correlated Reference Flow for Advanced Package Designs

Sigrity

As transistor device scaling gets closer and closer to physical limits, more and more companies have been looking beyond silicon and into multi-die approaches with advanced packaging to keep the innovation and speed performance trend going forward i...
- 9 May 2019
Analog/Custom Design: Virtuosity: The Top 3 Post-Layout Enhancements in Analog Design Environment

Arja H

Have you ever wanted to sweep DSPF files across corners, plot terminal current and voltage and ensure that the simulator name maps correctly to the schematic name in Virtuoso ADE Assembler and Virtuoso ADE Explorer? If so, IC6.1.8 ISR3/ICADVM12.8 ISR3 will be the release for you.
- 9 May 2019
Breakfast Bytes: Intel at Linley

Paul McLellan

At the recent Linley Spring Microprocessor Conference, there were two presentations by Intel about deep learning. The first was by Ian Steiner, the lead architect for Cascade Lake. The second was by Carey Kloss, the VP of Hardware for the AI products...
- 9 May 2019
Verification: Concurrent Actions in Specman: Part 2

teamspecman

In the previous blog: Concurrent Actions in Specman, we discussed the existing options: all of (which awaits completion of all branches) and first of (which terminates at the first completion of any branch). In 19.03 we added enhancement on top of these existing options, we made them more dynamic.

In all the examples in the previous blog, the number of branches was constant (all the examples used 2 branches). What if…
- 8 May 2019
Breakfast Bytes: How Do Out-of-Order Processors Work Anyway?

Paul McLellan

I've been meaning to write a post on how out-of-order processors work, but one challenge is to make the diagrams that are necessary to make it clear. Well, Jon Masters of Red Hat gave the keynote on the second day of the Linley Spring Microproces...
- 8 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Limitations of Scan Compression QoR

References4U

In this week's Whiteboard Wednesdays video, Scan Compression reduces the digital IC test time and data volume by orders of magnitude, but the technology’s limitations prevent achieving higher compression ratios. Distinguished engineer Rohit Kapur explains the different limiters of compression QoR and impact on scan design. To learn about the Cadence Modus DFT Software Solution, visit the product page at https://www.cadence…
- 7 May 2019
The India Circuit: A Special Day for Cadence India

Madhavi Rao

A few days ago, Cadence Bangalore, Noida and Pune sites had the opportunity to participate in a worldwide CSR initiative in collaboration with the NGO Rise Against Hunger (RAH). To celebrate our 30th Anniversary as a company, Cadence is partnering wi...
- 7 May 2019
Breakfast Bytes: JasperGold: the Next Generation

Paul McLellan

Formal verification has gone through a number of eras. In the early 1990s, it was an area mostly of academic interest, only able to handle toy problems. Then, in 1994, was the infamous FDIV bug. As Intel's Bob Bentley said at the 2012 Jasper User...
- 7 May 2019
Analog/Custom Design: Virtuoso Video Diary: What's New in Reliability Setup

Udit Rajput

Read this blog to know about the enhancements made to the reliability options form and to the overall reliability setup
- 7 May 2019
Breakfast Bytes: Statistical Power...or Why You Shouldn't Be Allowed to Turn Right on Red

Paul McLellan

I wrote last Friday in my post TSMC: Zero Excursion, Zero Defect about the statistical processes that are essential in semiconductor manufacturing to get high yield, and to catch any issues that arise early enough to fix them. I suspect that hig...
- 6 May 2019
Digital Design: A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

Priya E Joseph

“It’s not what it is, it’s about what it can become”
-The Lorax by Dr. Seuss

Have you recently reached out to open your car and received an unexpected shock…zap! There are no financial or health implications if the door handle of your car zaps you, but an Electrostatic Discharge (ESD) zap event can instantly destroy devices worth billions of dollars. Today, we are aware of the destructive…
- 5 May 2019
Breakfast Bytes: Sunday Brunch Video for 5th May 2019

Paul McLellan

https://youtu.be/ICpG3ouDIyQ Made at Nathan's Tesla (camera Sean) Monday: Andy Bechtolsheim: 85 Slides in 25 Minutes, Even the Keynote Went at 400Gbps Tuesday: Tesla Drives into Chip Design Wednesday: Linley Gwennap's Deep Dive into Deep Lear...
- 5 May 2019
System, PCB, & Package Design : BoardSurfers: Make Menus Your Own – Customizing Menus and Toolbars with Things You Use Daily

Tyler

Flexibility and the ability to customize the software/environment to your own personal needs is a definite strength of Cadence® software, and the Allegro® platform is no different. Whether you are developing your own SKILL program to make a detailed flow easier; automating a tedious, but routine, task; or just reordering commands in the menu to match your usage flow, Allegro offers you what you need. Best of all, it comes…
- 3 May 2019
PCB、IC封装：设计与仿真分析: 电路/硬件设计工程师如何选择原理图设计工具

TeamAllegro

当谈到在EDA领域选择原理图设计工具时，没有人可以找到万能的解决方案。多变的因素加之不尽相同的个人偏好，使得“最好的原理图设计工具是什么？”这个问题始终没有一个统一的答案。目前市面上的工具基本都可以完成大多数设计工作，甚至有些工具可能看起来还极其相似。在这种情况下，某一种产品能否脱颖而出则是非常主观的，简单易用、兼顾效率，成为了是否受用户欢迎的关键决定因素。通常，电路/硬件设计工程师在进行产品比较时会进行以下评估和考虑： space 使用工具之前，我需要预先学习...
- 3 May 2019
Breakfast Bytes: TSMC: Zero Excursion, Zero Defect

Paul McLellan

At the recent TSMC Technology Symposium, JK Wang, the SVP of fab operations, talked about Manufacturing Excellence. There were two parts to this: Capacity ramping and new fab status The pursuit of quality excellence Capacity Ramping and New Fab Sta...
- 3 May 2019
System, PCB, & Package Design : IC Packagers: Coming Soon to a Blog Near You…

Tyler

What is new in the Cadence® SiP Layout and APD tools? Is there reason to get excited to pick up the most recent HotFix of 17.2 (or update from release 16.6 to 17.2 at all)? The answer is a most emphatic YES. Join us as we start our jo...
- 2 May 2019

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