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Latest Blog Posts

  • 定制IC芯片设计 : Virtuosity: 模拟设计环境中的最重要的3个后仿改进功能

    Arja H
    Arja H
    今天的博客重点介绍了后仿流程的最新增强功能。 这些增强功能解决了许多长期存在的问题,例如原理图和版图命名的匹配,绘制端口电压和DSPF文件扫描。 这个博客是我们每周发布两次 - 周二和周四 - 的迷你博客系列的一部分,以涵盖Virtuoso®ADE Assembler,Virtuoso® ADE Explorer和Virtuoso® Visualization and Analysis中刚刚发布的功能。 请继续关注更多此类有趣的博客。 你有没有想过扫描不同Corne...
    • 18 Jul 2019
  • Breakfast Bytes: Orchestras, Degrees, and Choice

    Paul McLellan
    Paul McLellan
    Did you read about how orchestras started to do blind auditions where the players were behind a curtain? And how the result was lots more women hired into orchestras once the biased hiring committees couldn’t act on their prejudices…wome...
    • 18 Jul 2019
  • Analog/Custom Design: Tales from DAC: The New Spectre Simulator Is Here!

    XTeam
    XTeam

    If you’re doing circuit simulation anywhere in the world, you’re probably already familiar with the Cadence Spectre® simulator. The Spectre simulator is an accurate and high-performance SPICE circuit simulator that has established itself as the golden reference analog simulation over many years of use by designers. Now, with smaller geometries and denser chip designs, requiring more performance and capacity, the Spectre…

    • 17 Jul 2019
  • Breakfast Bytes: Intelligent System Design for Automobiles of the Future

    Paul McLellan
    Paul McLellan
    There's a lot going on in the automotive market. The three big things are electric traction, autonomous driving, and shared mobility. Cadence is holding their second annual Automotive Design Summit on July 30 in San Jose, where all aspects of aut...
    • 17 Jul 2019
  • System, PCB, & Package Design : BoardSurfers: Avoid Iterations with Your Manufacturing Partner – Detect and Address DFM Issues in the Design Phase Using DesignTrue DFM

    mrigashira
    mrigashira

     Some things are rare, good or bad, but they do happen from time to time. And, some happen so regularly, we often take them for granted if good or learn to live with them if bad. But should we? For example, you send out your design for fabrication and the CAM (computer-aided manufacturing) engineer runs a high-end design for manufacturability (DFM) analysis software. The CAM engineer sees DFM issues (almost always!). Now…

    • 16 Jul 2019
  • Whiteboard Wednesdays: Whiteboard Wednesdays – What is Happening at the USB IF Standards Meetings?

    References4U
    References4U

    In this week’s Whiteboard Wednesdays video, Jacek Duda talks about the next-generation standard, USB4.  What are the benefits? Overlap with existing USB standards? How does it compare with USB 3.x? Watch the video.

    https://youtu.be/sKHF8xB-NBk

    • 16 Jul 2019
  • System, PCB, & Package Design : IC Packagers: Bend in Both Directions with J-Loop Bond Wires

    Tyler
    Tyler
    Let’s talk about wire bonding for a quick minute. Still a favorite for many of you, bonding is a cheap way to connect your die to the top layer of your package (or to a lead frame, if that’s what you’re using). A 3D wire is connecte...
    • 16 Jul 2019
  • Breakfast Bytes: GLOBALFOUNDRIES After the Pivot

    Paul McLellan
    Paul McLellan
    At SEMICON West I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to get an update on what is going on since the “pivot”. The Pivot The pivot was the decision last year to pull back from 7nm and EUV development and focus their process ...
    • 16 Jul 2019
  • 定制IC芯片设计 : Virtuoso 视频日记: Reliability Setup 的新功能

    Udit Rajput
    Udit Rajput
    今天的博客重点介绍了可 reliability options 表单和整体 reliability setup 的增强功能。这个博客是我们迷你博客系列的一部分。我们会在每周二,周四各发布一次。我们的博客会涵盖 Virtuoso® ADE Assembler, Virtuoso® ADE Explorer 和 Virtuoso® Visualization and Analysis 中刚刚发布的功能。请继续关注更多此类有趣的博客。. 您是否曾使用 Rel...
    • 16 Jul 2019
  • Life at Cadence: Cadence and the Expanding Presence of Women in Tech Conferences

    FormerMember
    FormerMember
    Cadence sponsors several different tech conferences throughout the year. We use these events as an opportunity to allow employees to take a day out of our normal work routine to network, learn, and develop as leaders—but more importantly, so we...
    • 15 Jul 2019
  • SoC and IP: Is the Role of Test Chips Changing at Advanced Foundry Nodes?

    TomWong
    TomWong

    Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs.

    Semiconductor designers have long been making test chips to validate…

    • 15 Jul 2019
  • Breakfast Bytes: Will American Scooters Follow Chinese Bikes?

    Paul McLellan
    Paul McLellan
    I spent the July 4 weekend in San Diego. My public service announcement is that if you go to San Diego, the first thing you should do is buy a week pass to all the museums in Balboa Park, and add on a discount admission to the zoo if you plan to...
    • 15 Jul 2019
  • Analog/Custom Design: Virtuoso Meets Maxwell: Learn Your Moves – We’re Doing an Edit-in-Concert

    Steve PDK Lee
    Steve PDK Lee
    This blog showcases the Edit-in-Concert technology available in the Cadence Virtuoso RF Solution, which lets designers view and edit die packages and their corresponding die layouts synchronously.
    • 14 Jul 2019
  • Verification: How to Verify Performance of Complex Interconnect-Based Designs?

    Thierry Berdah
    Thierry Berdah

    With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions…

    • 14 Jul 2019
  • Breakfast Bytes: Sunday Brunch Video for 14th July 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/HO3cViPU6Mw Made at Slovensky Raj, Slovakia (camera Gary Bengier) Monday: Carry: From Logarithms to Mechanical Calculators Tuesday: Carry: Babbage's Engines Wednesday: Carry: Electronics Thursday: NXP: Can Silicon Valley Rea...
    • 14 Jul 2019
  • Breakfast Bytes: The Mercedes Benz Museum and the Invention of the Automobile

    Paul McLellan
    Paul McLellan
    Recently, I was in Stuggart, Germany. This is the home to the headquarters of both Daimler-Benz (or Daimler-Chrysler as it now is) and also Porsche. Both companies have fascinating museums. The thing that makes them especially interesting is that so ...
    • 12 Jul 2019
  • PCB、IC封装:设计与仿真分析: Cadence LPDDR4设计IP通过TSMC 16FFC FinFET 车规工艺验证

    Sigrity
    Sigrity
    本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC”。 space 今年4月份,Cadence宣布其LPDDR4/4X存储器IP子系统通过ISO 26262 ASIL C认证: “楷登电子(Cadence公司,NASDAQ:CDNS)今日宣布,采用TSMC16nm FinFET Compact(16FFC...
    • 12 Jul 2019
  • Analog/Custom Design: Virtuosity: Device-Level Routing for Advanced Nodes – Using Generate Trunks

    Parula
    Parula
    The Trunk Generation feature is the founding piece that offers incremental productivity improvement with automation over Pin to Trunk, while still providing all the customizable options in the Pin to Trunk flow.
    • 12 Jul 2019
  • Breakfast Bytes: NXP: Can Silicon Valley Really Crack the Automakers' Code?

    Paul McLellan
    Paul McLellan
    The second panel at the recent NXPConnect was about Silicon Valley versus traditional carmakers (OEMs in car industry terminology). The first panel I covered recently in NXP: Self-Driving Cars: What's the Payoff for Carmakers? Can Silicon Va...
    • 11 Jul 2019
  • VPLP Design: Revolutionizing Hydrofoil Design with Advanced CFD Simulation Technology

    Computational Fluid Dynamics: VPLP Design: Revolutionizing Hydrofoil Design with Advanced CFD Simulation Technology

    AnneMarie CFD
    AnneMarie CFD
    Hydrofoils have unleashed the speed of sailing boats since the last two America’s Cups and are exclusively designed with CFD. The French company VPLP Design is at the cutting edge of the hydrofoil concept and has worked with Alex Thomson Racin...
    • 11 Jul 2019
  • 定制IC芯片设计 : Virtuosity: 过滤波形

    Arja H
    Arja H
    在接下来的几周内,Virtuosity和Virtuoso Video Diary博客将重点关注Virtuoso®ADE Assembler, Virtuoso®ADE Explorer 和Virtuoso® Visualization and Analysis中刚刚发布的功能。因为我们有很多有趣的新增强改进和功能可供讨论,我们将在每周的周二和周四各发布一次博客。今天的博客是ADE迷你博客系列的第二篇。本博客将重点介绍现在可用于Virtuoso® Visualiz...
    • 11 Jul 2019
  • Breakfast Bytes: Carry: Electronics

    Paul McLellan
    Paul McLellan
    The last two days I have written about carry in mechanical calculating devices. See my posts Carry: From Logarithms to Mechanical Calculators and Carry: Babbage's Engines. We have similar problems in designing electronics. Most microprocessors d...
    • 10 Jul 2019
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Cloud-Hosted Design Solution – a Full-Service Cloud Offering

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Jeff Critten describes the key benefits of the Cadence® Cloud-Hosted Design Solution in providing a total solution for companies seeking to move entire electronic design projects to the cloud.

    https://youtu.be/CxvvOgo0ZTQ

    • 9 Jul 2019
  • Verification: AMBA Adaptive Traffic Profiles: Addressing The Challenge

    DimitryP
    DimitryP

    Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving.  With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex systems…

    • 9 Jul 2019
  • System, PCB, & Package Design : BoardSurfers: Look Before You Leap - Verifying Footprints in the Design Capture Phase

    mrigashira
    mrigashira
    View the footprints of symbols during design entry in Capture: verify the footprint and land pattern dimension before exporting your design to a board layout tool, such as PCB Editor,
    • 9 Jul 2019
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