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System, PCB, & Package Design : IC Packagers: Coming Soon to a Blog Near You…

Tyler

What is new in the Cadence® SiP Layout and APD tools? Is there reason to get excited to pick up the most recent HotFix of 17.2 (or update from release 16.6 to 17.2 at all)? The answer is a most emphatic YES. Join us as we start our jo...
- 2 May 2019
Analog/Custom Design: Virtuosity: Filtering Plots!

Arja H

If you're a regular reader of the Virtuosity series, you'll have seen a few blogs recently on filtering in Virtuoso ADE Assembler and Virtuoso ADE Explorer. Well, we've extended this capability and the same filters are now available for your plots in Virtuoso Visualization and Analysis.
- 2 May 2019
Breakfast Bytes: TSMC: Specialty Technologies

Paul McLellan

What is a "specialty technology"? Kevin Zhang, the VP of business development, told us at the recent TSMC Technology Symposium: If Yuh-Jier Mii doesn't talk about it, then it's a specialty technology Yuh-Jier Mii is the head of technology deve...
- 2 May 2019
Verification: Cadence at the Red Hat Summit--Come See Xcelium in Action!

XTeam

The Red Hat Summit is coming around to Boston this year, and it’s only a few short days away. Cadence has a demo at the Marvell booth (that’s #418-1), and we’ll be there from 3-7 PM on Wednesday, May 8^th. There, we’ll be showing off our Arm-server technology by demoing Xcelium. Be sure to stop by!

Cadence and Arm have worked together to create solutions that optimize power, performance, and area…
- 1 May 2019
Verification: Cadence at the HOST Symposium: Come See What We're Doing!

XTeam

The HOST Symposium is returning for its 12^th year, and general registration is open now. The IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) aims to accelerate and assist the development of hardware-based security technologies.

With the advent of Internet-of-Things (IoT) devices, new avenues of attack have opened up for nefarious hackers—what was previously focused on computers, defense, automotive…
- 1 May 2019
Breakfast Bytes: Linley Gwennap's Deep Dive into Deep Learning

Paul McLellan

At the recent Linley Spring Microprocessor Conference, Linley Gwennap kicked off with the opening keynote on what is clearly the biggest thing to hit processors in a long time: deep learning. Linley started with an overview of deep learning and the l...
- 1 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - SIMD Capability of B10 B20 and Some Associated Vector Processing Units

References4U

In this week's Whiteboard Wednesdays video, Pierre-Xavier Thomas shows some of the processing units of the B10/B20 supporting the SIMD architecture in the context of the operator support.

https://youtu.be/-620ZPxaYf8
- 30 Apr 2019
Analog/Custom Design: Spectre Tech Tips: Measuring Noise in Digital Circuits

RF Rich

As a designer, verification engineer, or CAD expert, you use Spectre APS for analyzing your designs. Sometimes, you use Spectre to measure noise in digital circuits. Are you confused which method to use for noise measurement since Spectre provides different methods for measuring noise? This blog discusses the different noise measuring methods and explains why they may provide different results.
- 30 Apr 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR3 and ICADVM18.1 ISR3 Now Available

Virtuoso Release Team

The IC6.1.8 ISR3 and ICADVM18.1 ISR3 production releases are now available for download.
- 30 Apr 2019
Breakfast Bytes: Tesla Drives into Chip Design

Paul McLellan

I've said for a couple of years that high-end automotive companies are going to have to do what the high-end mobile companies did, and build their own application processors. It will be the only way for them to get differentiation and built a pro...
- 30 Apr 2019
Verification: Specman Linting and the all_unique Method

teamspecman

Sorting according to pointers- why?
One of the best practices that you need to follow when using Specman or any other tool is to use a linting tool on a regular basis to catch bugs early. In Specman, we frequently add additional e checks to HAL (Cadence linting tool) based on the customer issues that can be avoided or caught during linting.

For instance, in 19.03, among few other linting checks, we planned to add a check…
- 29 Apr 2019
Breakfast Bytes: Andy Bechtolsheim: 85 Slides in 25 Minutes, Even the Keynote Went at 400Gbps

Paul McLellan

Andy Bechtolsheim likes to go fast. He famously had to rush off to a meeting but wrote Sergey and Larry $100K check to fund Google anyway, with no paperwork. At the keynote at CDNLive, he presented The Road to 400G Networking. He had 85 slides and 25...
- 29 Apr 2019
定制IC芯片设计 : Virtuosity: 在IC6.1.7 / ICADV12.3 ISR期间，我在Virtuoso可视化和分析以及ADE中遇到了什么?

Rashmi G

也许你一直被困在一个使用旧版Virtuoso 的项目上，也许你只是订阅了这些博客，或者你是Virtuoso的新用户，也许你不知道有哪些新的酷炫功能在 IC6.1.7 / ICADV12.3 ISR 的过程中添加了。我们已经添加了大量的增强功能，数量超过1600！我不能在这里详述所有这些内容，但我将概述 Virtuoso® ADE Assembler，Virtuoso® ADE Explorer 和 Virtuoso® Visualization and Analy...
- 28 Apr 2019
PCB、IC封装：设计与仿真分析: 了解AMI与IBIS之后需要知道：如何轻松完成DDR5设计

Sigrity

本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章"AMI for DDR5 Made Easy"。上一篇文章介绍了IBIS和AMI，并提到了行业内正在发生的一个重大变化： DDR5标准将（间接）授权使用AMI模型。 DDR5 在预计将于今年发布的DDR5标准中，DRAM将被指定涵盖DFE（判决反馈均衡）能力。而在实践中，DFE建模就意味着创建和使用AMI模型。实际上，近十年来用于分析串行链路的技术正在扩展应用到并行存储器接口领域。然...
- 26 Apr 2019
Analog/Custom Design: Virtuosity: Cdsenv Editor – Simplifying Virtuoso Customization

Sucharita

Customization is the need of the day. From picking an ice cream flavor to outfitting a premium car, we all want a product customized according to our needs and expectations.

Virtuoso users are no exception.

Yes, you can customize many features in the Virtuoso environment by changing values of variables that control these features. These variables stored across various .cdsenv files are shipped with each Virtuoso release…
- 26 Apr 2019
Breakfast Bytes: TSMC Technology Roadmap

Paul McLellan

Earlier this week it was the TSMC Technology Symposium. Here's my first post, summarizing TSMC's technology roadmap. As I do every year, I start with the caveat that this is all done from my notes, recording and photography is banned, and the...
- 26 Apr 2019
System, PCB, & Package Design : How to Accelerate Your Thermal Aware PI Design?

Sigrity

In modern electronic systems, there may be tens to hundreds of DC rail voltages used in the system, with voltage levels, for example, ranging from 48V/24V to 3.3V, 1.8V, 1.2V and even as low as 0.8V. Usually these systems will have a few input ...
- 25 Apr 2019
System, PCB, & Package Design : BoardSurfers - Aerials and Bails: How to Hide the Design Path in Art File

Monika

Before manufacturing, PCB fabricators analyze Gerber data to verify if it is manufacturable or not. If the artwork data meets the requirement, it is processed to make it usable by production tools and equipment. The various stages of data analysis and processing are automated at the manufacturer's end. Depending on the PCB maker you are working with, you may need to create artwork data files per their requirement.…
- 25 Apr 2019
Breakfast Bytes: 8 Things to Know about CDNLive EMEA

Paul McLellan

It's CDNLive EMEA! Well, not today, Monday, Tuesday and Wednesday, May 6 to 8 at the Infinity Hotel in Unterschleißheim (in the suburbs of Munich near the airport). I will be there and will write about some of the presentations. ...
- 25 Apr 2019
Computational Fluid Dynamics: BMT Specialized Ship Design: Ship Resistance Validation with Fluid Dynamics Simulation

AnneMarie CFD

At BMT Specialised Ship Design (formerly BMT Nigel Gee), the process for vessel resistance and speed calculation is broadly divided in: the parametric optimization phase, hull form optimization phase, and, when suitable to the project, experimental t...
- 23 Apr 2019
定制IC芯片设计 : Virtuosity：在Virtuoso可视化和分析中阅读矢量文件

Vani V

在IC6.1.8和ICADVM18.1之前，要查看数字和模拟波形以及应用的激励，必须使用数字和模拟求解器进行仿真。这可能是一个耗时的过程。但是，现在您可以将数字激励文件直接读入 Cadence® Virtuoso® 可视化和分析，即ADE波形窗口。此外，您可以使用激励绘制模拟波形。 ADE波形窗口支持读取以下格式的矢量文件 - 值更改转储（VCD）和数字矢量文件（VEC）。这些矢量文件可以像其他文件一样通过结果浏览器打开。矢量文件可以直接读入ADE波形窗口，数字波形和带激...
- 23 Apr 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Scan Compression Fundamentals

References4U

In this week's Whiteboard Wednesdays video, Industry expert Rohit Kapur introduces the basic concepts of digital IC scan compression. Topics explained include the impacts of test application time and test data volume on test cost and the problems solved by implementing scan compression. To learn about the Cadence Modus DFT Software Solution, visit the product page at https://www.cadence.com/modus

www.youtube.com/…
- 23 Apr 2019
Breakfast Bytes: ESD Alliance Evening with Paul Cunningham

Paul McLellan

Paul Cunningham was interviewed by Jim Hogan at the latest ESD Alliance "fireside chat". (Ever since Lip-Bu's fireside chat at DAC was interrupted by the fire-alarms due to a real fire, I've been a little wary of that name.) Jim said that he'd wanted...
- 23 Apr 2019
Breakfast Bytes: Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC

Paul McLellan

Last week, Cadence announced the certification of its LPDDR4 IP in TSMC's 16nm automotive process. The opening paragraph of the press release actually says: Cadence Design Systems, Inc today announced that the Cadence LPDDR4/4X memory IP su...
- 22 Apr 2019
定制IC芯片设计 : Virtuosity：模拟计划和覆盖环境（SPACE） - 简介

Rashmi G

随着工艺节点缩小到小于 28 纳米，模拟设计的复杂性正在迅速增加。这种复杂性导致了大量的工作条件（工艺，电压和温度，通常称为 PVT），在仿真过程中必须考虑这些条件，以确保您的电路性能，并确保在同一工艺节点上设计的所有不同设计模块当拼凑在一起时会工作正常。这给负责 Sign-off 不同设计模块的项目经理带来了另一个挑战。通常，分配设计模块的团队将设计要求划分为子模块，并将每个子模块的设计分配给各个工程师。然后，项目经理需要确保在正确的工作环境，电压值上模拟所有设计模块，并使用适当版本的模型...
- 21 Apr 2019

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