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Analog/Custom Design: Virtuosity: Spring-Cleaned Virtuoso Doc Closet

Rishu Misri Jaggi

Most of us know how a spring-cleaned house can look like. But, do you know how the spring-cleaned Virtuoso documentation closet could look like?
- 19 Apr 2019
Breakfast Bytes: Online Regulations in England and Australia

Paul McLellan

Everyone in technology, even as far down the value chain as EDA and semiconductors, should understand the implications of how the technology they work on is being used upstream—in particular, how technology interacts with the social a...
- 19 Apr 2019
Breakfast Bytes: SEMICON China: 100,000 Visitors

Paul McLellan

China is hugely important for electronics in general and semiconductor in particular. You can't really appreciate it from the bubble of Silicon Valley, you have to go there. For the second year, I attended SEMICON China in Shanghai (conveniently ...
- 18 Apr 2019
Breakfast Bytes: Genus and Innovus: Compus and iSpatial

Paul McLellan

Yesterday I covered the first part of Chuck Alpert's presentation on the upcoming-any-day-now release of Genus (19.1 i you're counting). Today I'll dig into the details a bit more. Compus In the new release, there is a next-generation compiler calle...
- 17 Apr 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - CloudBurst - Fast, Painless, Proven Solution for Hybrid Cloud Environments

References4U

In this week's Whiteboard Wednesdays video, Craig Johnson explains the reasons behind the addition of the CloudBurst Platform to the Cadence® Cloud Portfolio and its usefulness in serving peak demand in hybrid cloud environments.

https://youtu.be/TjlOTW31fkE
- 16 Apr 2019
Breakfast Bytes: Genus and Innovus: Together at Last

Paul McLellan

Yesterday I wrote about a presentation at CDNLive Silicon Valley Qualcomm: Bring Me My Snapdragons, where Pavan Patibanda explained the methodology that they use for having a workable methodology for designing Snapdragon SoCs. The following...
- 16 Apr 2019
定制IC芯片设计 : Virtuosity: 运行计划助手的新功能-第一部分

NamrataM

事实证明，Virtuoso ADE Assembler 中的运行计划助手是最流行的功能之一。它提供了在单个会话中创建多个设置变体的功能，每个运行都有自己的设置详细信息，这些详细信息覆盖活动设置中的设置。只需单击一次，就可以对运行计划中定义的所有设置进行仿真. 如果没有依赖关系，则同时生成结果.
- 16 Apr 2019
System, PCB, & Package Design : BoardSurfers: Place Replicate to Increase IP Reuse and Decrease Design Time

Tyler

Once you have successfully designed and optimized an area of your substrate today, how do you leverage your tool to reuse your work across the rest of your current design – or apply it to other similar layouts in your queue?

If you have the good fortune to use the Cadence® Allegro® layout tools, you should turn to the place replicate interface. Whether you want to leverage just the symbol placement, incorporate…
- 15 Apr 2019
Breakfast Bytes: Qualcomm: Bring Me My Snapdragons

Paul McLellan

I'm writing this before the Game of Thrones season opener last night. But since last season ended with an undead dragon demolishing the wall, I'm pretty sure dragons will play a big part. More relevant to semiconductors is Snapdragon, Qualcomm's...
- 15 Apr 2019
Breakfast Bytes: Sunday Brunch Video for 14th April 2019

Paul McLellan

https://youtu.be/ml397HeOHcc Made at Steve Brown's Tesla in Cadence parking lot (camera Steve Brown) Monday: Driving Dangerously Tuesday: Barefoot in a CloudBurst: Tempus on 2000+ CPUs Wednesday: TI's Experience Taping out with Pegasus Thursd...
- 14 Apr 2019
PCB、IC封装：设计与仿真分析: 如何利用Virtuoso平台高效精确地设计一款射频前端模块电路（一）

SDA China

作为一名射频前端设计的工程师，大家肯定都有过这样的疑惑：我究竟是做IC设计的，还是做板级电路设计的？如果是前者，为什么我们做仿真不跑corner，不跑蒙特卡罗，甚至连个精确的晶体管模型都没有，每天要花大量的时间在实验室里面做调试工作。锡膏，烙铁，镊子是我们每天都要见到的好朋友。如果是后者，我交付给客户的必须是一片没有任何瑕疵的芯片，每一个管脚都要正确定义，每一个指标都要严格过关，甚至还要帮助客户负责外围电路的设计和调试。但不知大家想过没有：我们为什么会有这样的疑惑？为什么我们不能像普通的CMO...
- 12 Apr 2019
Breakfast Bytes: Brad Brim and the History of Signal Integrity

Paul McLellan

I sat down with Brad Brim recently. He was retiring from Cadence literally the following day. He has worked on signal integrity his entire career, which spans the period from signal integrity not really being anything at all in the digital world...
- 12 Apr 2019
System, PCB, & Package Design : Power Plane Loop Inductance Guidance for PDN Designers

Sigrity

Gaining an understanding of power plane loop inductance is important for efficient printed circuit board (PCB) designs. Unfortunately, board designers too often use inappropriate rules of thumb when laying out the power delivery network (PDN) ...
- 11 Apr 2019
Analog/Custom Design: Virtuoso Video Diary: Creating and Previewing Stimuli

Arja H

If you've ever tried to add stimuli to your design using the Stimuli form, you'll agree it needed a revamp. Most people tend to use a vsource or isource component or a file to set up stimuli. But wouldn't it be nice if you could create a library of stimuli to share between designs, and to preview your stimuli waveforms without having to simulate the entire circuit. Well in Virtuoso ADE Assembler and Virtuoso ADE Explorer…
- 11 Apr 2019
Breakfast Bytes: Superhuman Photonic Design

Paul McLellan

I recently came across an article titled Generative Design Could Radically Transform the Look of Our World. No, the article wasn't about semiconductor design... at least not yet. It was about architecture. And chairs. For example, the image ...
- 11 Apr 2019
Breakfast Bytes: TI's Experience Taping out with Pegasus

Paul McLellan

At the recent CDNLive Silicon Valley, Kyle Peavy of Texas Instruments (TI) presented Cadence Pegasus Physical Verification: A Customer Tapeout Experience, along with Cadence's Digo (Dibyendu) Goswami. Obviously, just based on the title, TI taped...
- 10 Apr 2019
Analog/Custom Design: Virtuoso Video Diary: Tune In to the MPT Video Channel

KomalJohar

Tune In to the MPT Video Channel to check out a wide range of features easily accessible through the MPT toolbar.
- 9 Apr 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - 3X Faster Design Closure with Quantus Integrated Virtual Metal Fill

References4U

In this week's Whiteboard Wednesdays video, Senior Product Engineering Manager Varun Raj Garapati outlines why traditional metal fill insertion, usually at the signoff stage, is not recommended for FinFET designs to ensure fastest design closure. The Quantus Integrated Virtual Metal Fill (IVMF) solution offers designers the ability to run virtual metal fill much earlier in the design during post-route optimization stage…
- 9 Apr 2019
Breakfast Bytes: Barefoot in a CloudBurst: Tempus on 2000+ CPUs

Paul McLellan

Barefoot Networks gave a couple of presentations at the recent CDNLive Silicon Valley. Both presentations were about the latest member of their Tofino family of ASICs. This networking chip has a throughput of 12.8Tbps and is fully programmable. It ha...
- 9 Apr 2019
Breakfast Bytes: Driving Dangerously

Paul McLellan

I've written a few times before about the fragility of neural networks, for example in last year's post Fooling Neural Networks. There is an unstated assumption underlying the training of neural networks that the environment is benign, a...
- 8 Apr 2019
Breakfast Bytes: Sunday Brunch Video for 7th April 2019

Paul McLellan

https://youtu.be/DUu3M30lilE Made at CDNLive Silicon Valley (camera Sean) Monday: CloudBurst: The Best of Both Worlds Tuesday: Bringing Clarity to System Analysis Wednesday: Geoff Hinton, Yann LeCun, and Yoshua Bengio Win 2019 Turing Award Thursday: ...
- 7 Apr 2019
PCB、IC封装：设计与仿真分析: Chiplets——重新定义系统设计

Sigrity

当下，电子行业经历着系统设计的新范式转变：传统的单片SoC电子系统设计思路正逐渐转变为使用chiplets（即“小芯片”）和高级封装技术的多芯片设计方法。这种逆转思维为系统设计开启了一个新的时代。什么是chiplets和基于chiplets的系统？ Chiplets的概念其实已存在了几年，随着高级互连和封装技术的日趋成熟，人们对它的关注越来越大。Chiplets是已知的良好芯片，通常具有单一特定功能，并且包含具有小型微缓冲器的封装器、级别转换能力、启用测试，以及利用诸...
- 5 Apr 2019
The India Circuit: Simple Things You Can Do To Get Ahead In The Workplace

Madhavi Rao

Recently we were lucky to have two of the women vice presidents at Cadence – Karna Nisewaner from the Legal team and Alessandra Costa who leads the Field Engineering team in North America – visit India and have interaction sessions with o...
- 5 Apr 2019
Breakfast Bytes: RSA: Public Interest Technologists

Paul McLellan

Yesterday, I wrote about the first half of Bruce Schneier's keynote at the recent RSA Conference in San Francisco. Today, the second half, and the audience Q&A. If you work in security in any way, or just have some interest in the area, you o...
- 5 Apr 2019
Analog/Custom Design: Virtuoso Video Diary: Checking EM Compliance Before Creating Layouts

NamrataM

How about checking your designs for electromigration (EM) compliance before creating layouts? Why not? Read further to know more ...
- 4 Apr 2019

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