• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Community Forums
  3. Cadence Community
Cadence Community
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Site
  • Search
  • User
Find Other Members ►
Subscriptions
Get email delivery of the Cadence blog (individual posts).
  • Twitter
  • Facebook
  • LinkedIn
  • Google+

Community


Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

  • Digital Design: QoR with High-Level Synthesis. Can it really be better than hand-coded RTL?

    SeanDart
    SeanDart

    Whenever we talk to potential customers about Stratus HLS, we usually mention that many users get better quality of results (QoR) with a Stratus HLS flow than they did simply writing RTL by hand. Often, we are greeted with looks of skepticism or downright disbelief. We are usually asked the honest question:

    Can Stratus HLS really achieve better QoR than we can get using traditional RTL coding?

    I assure you that it can…

    • 2 Aug 2018
  • Analog/Custom Design: Virtuoso Video Diary: Single Schematic Flow in Virtuoso System Design Platform

    deeptig
    deeptig
    The Single Schematic Flow in Virtuoso System Design Platform simplifies the product usage. It allows you to generate a hierarchical schematic that can be used for simulations as well as for driving the layout of the package.
    • 2 Aug 2018
  • Breakfast Bytes: ITF: CFETs and New Interconnect

    Paul McLellan
    Paul McLellan
    At the imec technology forum (ITF) held the day before SEMICON West opened, two of the presentations were about future technologies, one focused on the FEOL, front-end-of-line, meaning the transistors. The other was focused on BEOL, back-end-of-...
    • 2 Aug 2018
  • Breakfast Bytes: How to Pitch a Journalist

    Paul McLellan
    Paul McLellan
    In the early part of my career, I was an engineer or an engineering manager. Then, I moved into operational management and marketing, which meant I spent a fair bit of my time talking to journalists. Without really planning it, when I found myse...
    • 1 Aug 2018
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 2

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Tom Hackett completes the story of the evolving von Neumann computer architecture and the adaptations driven by recent cloud computing challenges. The effort to overcome these challenges has led to the development of a new industry standard called the Cache Coherent Interconnect for Accelerators (CCIX).

    https://youtu.be/D8pzVq4uJ-E

    • 31 Jul 2018
  • Verification: Tales from DAC: How Altia Systems Used Xcelium to Bring New Life to Virtual Meetings

    XTeam
    XTeam

    We’re going to take a wild guess and say you’ve been in a meeting before. Maybe it was a virtual meeting—but those never really feel the same in person, do they? Attending a virtual meeting can feel cold and impersonal, especially since you can barely see everyone else. Everyone is there except you—and even then, saying you’re “there” is a bit of a stretch.

    Nowadays, though, there…

    • 31 Jul 2018
  • Breakfast Bytes: GLOBALFOUNDRIES' CTO State-of-the-Roadmaps

    Paul McLellan
    Paul McLellan
    At SEMICON I got to sit down with Gary Patton, the CTO of GlobalFoundries. They have a dual roadmap, with both 14nm FinFET (licensed from Samsung) going to 7nm (internally developed), and with the other track being FD-SOI (licensed originally from ST...
    • 31 Jul 2018
  • Breakfast Bytes: Dave Patterson on Becoming a Computer Scientist...and Going Directly to Happiness

    Paul McLellan
    Paul McLellan
    At SEMICON West, Dave Patterson (center) sat down for an interview with author John Markoff (left). Also on stage was Mark Hill (right), who is a professor at the University of Wisconsin, but he was one of Dave's early students at UC Berkeley. D...
    • 30 Jul 2018
  • Breakfast Bytes: Turning Fixed Costs into Variable Costs: Foundries and Clouds

    Paul McLellan
    Paul McLellan
    One trend that has been accelerating for a couple of decades is turning fixed costs into variable costs. Often this is what is behind outsourcing some capability. Sometimes it is driven purely by lower variable costs (let's hire a team in Shanghai) o...
    • 27 Jul 2018
  • Breakfast Bytes: Breakfast Bytes Guide to Armenia

    Paul McLellan
    Paul McLellan
    Every summer for a week I go hiking with a group of friends. We used to just go to Yosemite, but then we went to Alaska and hiked the Chilkoot trail (I have walked from the US into Canada...not sure if I count as an illegal alien). We did Kilimanjaro...
    • 26 Jul 2018
  • System, PCB, & Package Design : EE Thermal 101 – Thermal Basics for Electrical Engineers (Part 2 of 4)

    Sigrity
    Sigrity
    In part 1 of this blog series we discussed the duality between the electrical and thermal conduction domains.  In this blog, we’ll take a look at the three different modes of heat flow or heat transfer and relate these to thermal resistan...
    • 25 Jul 2018
  • Breakfast Bytes: What's For Breakfast? Video Preview July 30th to August 3rd 2018

    Paul McLellan
    Paul McLellan
    https://youtu.be/HoEoMWal_48 Coming from DARPA ERI Summit at Palace of Fine Arts, San Francisco (camera Frank Schirrmeister) Monday: Dave Patterson on Becoming a Computer Scientist...and Going Directly to Happiness Tuesday: GLOBALFOUNDRIES...
    • 25 Jul 2018
  • Breakfast Bytes: Trends, Technologies, and Regulations in China's Auto Market

    Paul McLellan
    Paul McLellan
    At "Ludwigsburg", officially the International Autombil Elektronik Kongress, there was a push this year to be more international. In particular, attendees last year had asked for a deeper perspective on what is happening in the largest auto...
    • 25 Jul 2018
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 1

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Tom Hackett traces the evolution of the von Neumann computer architecture through a series of adaptations intended to bypass processing bottlenecks that appeared as more and more demands were placed on computing systems.  This provides a historical lens with which to view the recent development of the CCIX interconnect standard.

    www.youtube.com/watch

    • 24 Jul 2018
  • Breakfast Bytes: Cadence Is MAGESTIC

    Paul McLellan
    Paul McLellan
    Today at the Electronic Resurgence Initiative (ERI) Summit in San Francisco, DARPA announced that Cadence was selected to support the Intelligent Design of Electronic Assets (IDEA) program, one of six programs with ERI to use advanced machine learnin...
    • 24 Jul 2018
  • Verification: Tales From DAC: How Syntiant Went From Zero to Tapeout in Six Months

    XTeam
    XTeam

    Here’s something to chew on:

    Syntiant is an AI startup involved in deep learning technology and semiconductor design. Their goal is to create exceptionally low-power designs for always-on devices, like those used in speech detection.

    Syntiant went from empty air to tapeout in six months.

    That sounds hard to believe, but it’s true. They got their first venture-capital funding in October of 2017, taped out initial…

    • 23 Jul 2018
  • Breakfast Bytes: Nicolas's Recipe for Digital Marketing in EDA

    Paul McLellan
    Paul McLellan
    This is the third (and final) post about the ESD Alliance workshop on digital marketing in EDA. The first two were Digital Marketing in EDA...with No Hands on the Wheel, and ESD Alliance Workshop on Digital Marketing. Here is Nicolas's detailed r...
    • 23 Jul 2018
  • Verification: Perspec Portable Stimulus Hands-On Workshop at DAC 2018

    Steve Brown
    Steve Brown
    Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised a hands-on workshop to learn about Accellera Portable Stimulus Specification (PSS) v1.0. But we made participants compete head to head, for prizes, and their pride! T...
    • 20 Jul 2018
  • Breakfast Bytes: What's For Breakfast? Video Preview July 23rd to 27th 2018

    Paul McLellan
    Paul McLellan
    https://youtu.be/KwrfcMtbMDM Coming from CDNLive Japan (camera Asushi Tanaka) Monday: Nicolas's Recipe for Digital Marketing in EDA Tuesday: Embargoed announcement Wednesday: Trends, Technologies, and Regulation in China's Auto Market...
    • 20 Jul 2018
  • Breakfast Bytes: CDNLive Japan: 対応ポートフォリオ

    Paul McLellan
    Paul McLellan
    As I said on Monday, I am in Japan this week for CDNLive. I haven't been in Japan for business since the year when I was CEO of Envis. Friday it's CDNLive Japan, held in the Yokohama Bay Hotel Tokyo. When I was told the hotel name, I'd never heard of...
    • 20 Jul 2018
  • Breakfast Bytes: Sigrity 2018—Into the 3rd Dimension

    Paul McLellan
    Paul McLellan
    Cadence has talked about System Design Enablement for the last few years, taking a more holistic view of designing a system. This means taking into account not just the chip(s) in the system, but also the packages, boards, and the software load that ...
    • 19 Jul 2018
  • Breakfast Bytes: Toshiba Electronic Devices & Storage Corporation and Interconnect Workbench

    Paul McLellan
    Paul McLellan
    I recently talked with Mr Takizawa of Toshiba Electronic Devices & Storage Corporation (TDSC) about their use of Cadence's Interconnect Workbench (IWB). IWB has been deployed on 6 completed ASIC projects, and a seventh that is still ongo...
    • 18 Jul 2018
  • Breakfast Bytes: The First Sushi I Ever Ate Was in Japan

    Paul McLellan
    Paul McLellan
    In the first installment, I wrote about why I had to visit Japan in 1983, and the semiconductor stuff I did there. Today, it's all the other stuff. Japanese Food When I went on this first trip to Japan, Japanese food was not common in the US (and...
    • 17 Jul 2018
  • Breakfast Bytes: VLSI's Secret Business...and a Trip to Japan

    Paul McLellan
    Paul McLellan
    This week it is CDNLive Japan on Friday July 20th. I will be there so obviously this will be my latest trip to Japan...but we will start by looking at my first trip to Japan. The first trip I made to Japan was in 1983. This was very early. If you hav...
    • 16 Jul 2018
  • The India Circuit: 7 Reasons Why Engineering Students in India Should Participate In The Cadence Design Contest!

    sangramjena
    sangramjena
    Recently, Cadence India announced the 13th edition of the Cadence Design Contest. Through this contest, Cadence provides a platform for students to showcase their design talent and serve as a stepping-stone to achieving greater things in their career...
    • 16 Jul 2018
<>
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information