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Latest Blog Posts

  • Cadence Integrates NVIDIA NIM Microservices into Its Design Process

    Corporate News: Cadence Integrates NVIDIA NIM Microservices into Its Design Process

    Corporate
    Corporate
    From semiconductors to pharmaceuticals, incorporating tailored AI applications into design has become crucial for accelerating the discovery process. However, using AI requires vast datasets for training, which necessitates safeguarding sensitive inf...
    • 8 Oct 2024
  • Is Liquid Cooling Right for Your Data Center?

    Data Center: Is Liquid Cooling Right for Your Data Center?

    MarkSeymour
    MarkSeymour
    We live in an exciting time—liquid cooling, which once seemed more trouble than it’s worth, is fast becoming an accepted and sought-after technology in the data center industry. That said, it’s still a complex technology to impleme...
    • 8 Oct 2024
  • Cadence Academic Network

    Academic Network: Bridging the Gap: Cadence and Bristol University Develop Industry-Ready Engineers

    Vinod Khera
    Vinod Khera
    Over the last two decades, telecommunications technology has undergone remarkable transformations: it has lowered societal barriers and bridged geographical distances, culminating in establishing an instantaneously connected global society. Informati...
    • 8 Oct 2024
  • Assumptions and Insights of k-epsilon Low Re Yang-Shih Turbulence Model

    Computational Fluid Dynamics: Assumptions and Insights of k-epsilon Low Re Yang-Shih Turbulence Model

    Gaurav
    Gaurav
    Key Takeaways A new time scale-based k-epsilon (k-ɛ) model for near-wall turbulence is discussed. In this model, is chosen as the turbulent velocity scale. The Kolmogorov time scale bounds the time scale. When this time scale is used to reformulate ...
    • 8 Oct 2024
  • Waveform of the Clock and Data at Receiver Input

    SoC and IP: Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem

    MBhatnagar
    MBhatnagar
    Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet designs and demonstrate high data rate performance in TSMC's 3nm technology
    • 7 Oct 2024
  • Using Voltus IC Power Integrity to Overcome 3D-IC Design Challenges

    System, PCB, & Package Design : Using Voltus IC Power Integrity to Overcome 3D-IC Design Challenges

    MSATeam
    MSATeam

     Advanced chiip designPower network design and analysis of 3D-ICs is a major challenge due to the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs).
    Cadence’s Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provide a fully integrated solution for early…

    • 7 Oct 2024
  • Creating Connections through Career Catalyst

    Life at Cadence: Creating Connections through Career Catalyst

    Dominique Topps
    Dominique Topps
    Early career employees Ankit Narasimhan, Jai Ganesh Iyer, Jhenkar Kallambella Suresh, Sanjukta Sheth, Viraj Ranade, Ishika Bhattacharya, and Kushagra Gupta, hailing from Cadence’s Custom IC & PCB Group (CPG), Silicon Solutions Group (SSG),...
    • 7 Oct 2024
  • First Major Toolbox for MATLAB/Simulink Model Deployment to Tensilica HiFi DSPs

    Corporate News: First Major Toolbox for MATLAB/Simulink Model Deployment to Tensilica HiFi DSPs

    Corporate
    Corporate
    Traditionally, developing software for digital signal processors (DSPs) involves a multi-step process: crafting the algorithm code in a specialized tool, adapting it for a specific domain, and implementing it onto the DSP. Given the growing demand fo...
    • 7 Oct 2024
  • Data center external airflow model

    Data Center: Tradeoffs in Managing Data Center External Airflow

    NaomiM
    NaomiM
    By Matthew Kaufeler, Senior Principal Product Engineer When you build a data center, your data hall design team needs to consider how your server rack layout impacts cooling while maximizing usable space. They must plan where to place cable and pipew...
    • 6 Oct 2024
  • encrypted chip

    Verification: Partial Header Encryption in Integrity and Data Encryption for PCIe

    Kunal Chhabriya
    Kunal Chhabriya
    Cadence PCIe/CXL VIP support for Partial Header Encryption in Integrity and Data Encryption.
    • 6 Oct 2024
  • Accessing Doctype Definitions in the Cadence Learning and Support Portal – pt 2

    Learning and Support: Accessing Doctype Definitions in the Cadence Learning and Support Portal – pt 2

    Sachin Nagpal
    Sachin Nagpal
    Hopefully, our blog Doctype definition and accessing them on Cadence Learning and Support Portal -1 was useful for you, and as promised, we are excited to present some other collaterals within our Cadence Learning and Support Portal (all listed under...
    • 4 Oct 2024
  • Deciphering the Potential of High-Fidelity CFD Simulations Across Industries

    Computational Fluid Dynamics: Deciphering the Potential of High-Fidelity CFD Simulations Across Industries

    Veena Parthan
    Veena Parthan
    The landscape of CFD is undergoing a novel shift with the emergence and application of high-fidelity simulations. These advanced simulations, particularly through large eddy simulations (LES), are setting new benchmarks in precision, accuracy, and efficiency across various industries.
    • 3 Oct 2024
  • CadenceCONNECT: Take the Heat Out of Your AI Data Center

    Data Center: CadenceCONNECT: Take the Heat Out of Your AI Data Center

    NaomiM
    NaomiM
    As we delve deeper into the AI era, data centers have become the backbone of technological progress. These high-density computing hubs, often called “AI factories,” are crucial for sustaining and accelerating advancements across various f...
    • 3 Oct 2024
  • International Women in AI Day: Creating More Opportunities for Women in AI

    Corporate News: International Women in AI Day: Creating More Opportunities for Women in AI

    Corporate
    Corporate
    In the rapidly evolving world of artificial intelligence (AI), diversity is not just a value—it's an imperative. International Women in AI Day, celebrated on October 1, shines a spotlight on the contributions and challenges faced by women ...
    • 1 Oct 2024
  • Cadence Doc Assistant

    Analog/Custom Design: Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer Part 3

    Priya Sriram
    Priya Sriram

    Welcome back to the Doc Assistant A-Z blog series!

    Since the launch of Doc Assistant, we've been gathering feedback and input from our customers regarding their experiences with our latest documentation viewer. My interaction with Ralf was particularly useful and interesting.

    Ralf is a design engineer who works on complex schematics and intricate layouts. For each release, he is challenged with the task of verifying…

    • 30 Sep 2024
  • Spectre 24.1 Release Now Available

    Analog/Custom Design: Spectre 24.1 Release Now Available

    SpectreReleaseTeam
    SpectreReleaseTeam
    The SPECTRE 24.1 release is now available for download at Cadence Downloads. For information on supported platforms and other release compatibility information, see the README.txt file in the installation hierarchy.
    • 30 Sep 2024
  • Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA

    SoC and IP: Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA

    Nayan Gaywala
    Nayan Gaywala

    Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environment. Locking is the most…

    • 30 Sep 2024
  • Jasper Formal Fundamentals 2403 Course for Starting Formal Verification

    Verification: Jasper Formal Fundamentals 2403 Course for Starting Formal Verification

    Amey Dahikar
    Amey Dahikar

    The course "Jasper Formal Fundamentals v24.03" introduces formal analysis to those who want to use formal analysis for design or verification. 

    To optimally benefit from this course, you must already have sufficient knowledge of the System Verilog assertions to be capable of writing properties for formal verification. Hence, this training provides a module on formal analysis to help cover this essential background…

    • 30 Sep 2024
  • Highlights from the CadenceLIVE India CFD Track

    Computational Fluid Dynamics: Highlights from the CadenceLIVE India CFD Track

    Veena Parthan
    Veena Parthan
    On September 13, CadenceLIVE India marked its second successful year in the computational fluid dynamics (CFD) domain, featuring an insightful CFD track at the Radisson Blu Hotel, Bangalore. The event showcased Cadence's remarkable expansion beyond ...
    • 26 Sep 2024
  • cadence_community_forums_thumbnail

    System, PCB, & Package Design : 10 Most Viewed Posts in Cadence Community Forum

    Renu Vibha
    Renu Vibha
    Community engagement is a dynamic concept that does not adhere to a singular, universal approach. Its various forms, methods, and objectives can vary significantly depending on the specific context, goals, and desired outcomes. Whether you seek assis...
    • 25 Sep 2024
  • Transforming Drug Discovery with Computational Methods

    Corporate News: Transforming Drug Discovery with Computational Methods

    Reela Samuel
    Reela Samuel
    The recent pandemic has highlighted the critical need for rapid and cost-efficient development of new medications. However, creating new drugs—whether small molecules, biologics, macrocycles, or degraders—is a lengthy and costly endeavor,...
    • 25 Sep 2024
  • DDR5 UDIMM Evolution to Clock Buffered DIMMs (CUDIMM)

    Verification: DDR5 UDIMM Evolution to Clock Buffered DIMMs (CUDIMM)

    Shyam Sharma
    Shyam Sharma

    DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per DIMM card. The highest speed…

    • 22 Sep 2024
  • Cadence Employee's 4,260km Walk to Support the Fight Against Cancer

    Life at Cadence: Cadence Employee's 4,260km Walk to Support the Fight Against Cancer

    Lautanen
    Lautanen
    Pierre-Alexis Desmares, Principal Applications Engineer at Cadence from France, is taking on a challenge by hiking the Pacific Crest Trail (4,260 km) within the USA alone, raising €1 per km for the League Against Cancer. You can donate here for ...
    • 19 Sep 2024
  • Improving Mesh Adaption with Fidelity CFD

    Computational Fluid Dynamics: Improving Mesh Adaption with Fidelity CFD

    Veena Parthan
    Veena Parthan
    This blog post explores the concept of mesh adaptation and the latest mesh adaptation features in Fidelity 2024.1, discusses its benefits, shares best practices, and highlights important considerations when using mesh adaptation in Fidelity 2024.1.
    • 18 Sep 2024
  • Introducing Fem.AI: Reshaping the Tech/AI Workforce for a More Equitable Future

    Corporate News: Introducing Fem.AI: Reshaping the Tech/AI Workforce for a More Equitable Future

    Nicole Johnson
    Nicole Johnson
    The Cadence Giving Foundation was founded in 2022 to support critical needs in communities around the world with a focus on access to STEM education, DEI in STEM, and climate and sustainability. We are excited to unveil an exciting initiative our tea...
    • 18 Sep 2024
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