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PCIe (Peripheral Component Interconnect Express) is a high-speed serial interconnect that is widely used in consumer and server applications. Over generations, PCIe has undergone diversified changes, spread across transaction, data link and physical layers. The latest PCIe 6.0 specification, too, has significant changes like the introduction of the flit concept, PAM4 signaling, L0p, shared flow control, and…

Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration) design? 

Keeping testability in mind when developing a chip makes it simpler to find structural flaws in the chip and make necessary design corrections before the product is shipped to users.

The DFT process might take many hours, days, or even weeks due to the increasing design complexity of today's system on chips. Techniques for DFT…

In the rapidly evolving landscape of data centers, ensuring cache coherence in multi-host environments is imperative. The Compute Express Link (CXL) 3.0 specification introduces a robust mechanism known as the Back-Invalidate feature to uphold cache coherence across multiple hosts and devices. This blog delves into the technical complexity of the Back-Invalidate feature, explaining how it contributes to the efficient…

The semiconductor landscape is undergoing a seismic shift as the demand for more powerful and energy-efficient electronic devices reaches new heights. In a recent panel discussion at CadenceLIVE Europe, featuring luminaries such as Kevork Kechichian from Arm, Paul Cunningham from Cadence, Norbert Schuhmann from Fraunhofer, Trent Uehling from NXP,  Davide Rossi from the…

Have you ever experienced the frustration of fixing a bug during the design stage only to discover additional bugs while trying to fix the existing one? As a verification engineer, this can be a common problem that can cause previously passing tests to fail suddenly, leaving your team to pick up the pieces. Ensuring the logic functionality early in the design is the holy grail of functional verification and debugging…

Most design teams use the schematic-driven connectivity-aware environment of Virtuoso Layout XL. However, due to the reuse of legacy designs, third-party tools, and the flexibility of the Virtuoso platform, a design can lose binding and connectivity.

Despite the layout being LVS clean, this loss of Virtuoso Layout XL compliance can result in incomplete or incorrect information in the design that can impact the layout…

We would now like to bring you another in-depth Training Webinar that will follow on from Achieving First-Time-Right Analog/RF/MS IC Design with Virtuoso Studio running on December 5th.

The new Virtuoso Studio custom IC design solution provides differentiating and innovative features, a reimagined infrastructure for unrivaled user productivity, and new levels of integration that stretch beyond classic design boundaries…