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Computational Fluid Dynamics: The Era of Fluid Simulations in Hollywood

Veena Parthan

VFX effects for fluid flow in movies are created using fluid simulation platforms that employ real fluid physics such as the Navier Stokes equation.
- 13 Apr 2022
Breakfast Bytes: DesignCon 2022: The 224G Show

Paul McLellan

At DesignCon, there is often a theme that comes through, and this year there were two: silicon photonics and 224G SerDes. I already covered the opening keynote in my post The Convergence of Photonic and Electronic ICs. Today, it is the turn of 224G. ...
- 13 Apr 2022
Analog/Custom Design: Virtuosity: Custom IC Design Flow/Methodology – Schematic Capture and Circuit Simulation

Ashish Patni

Read this blog for an introduction to the Custom IC Design methodology and the key design challenges that the methodology can help you address.
- 12 Apr 2022
Computational Fluid Dynamics: Meet Our Marine CFD Experts at the Euromaritime Exhibition

AnneMarie CFD

On June 28-30 2022, the Maritime Community meets again in Marseille at this biennial meeting of blue growth industrialists. Cadence CFD will be there and is looking forward to meeting you! Visit our booth or book an appointment with one of our experts (link in this article)
- 12 Apr 2022
Breakfast Bytes: Secure Before You Fabricate

Paul McLellan

One thing that I have come into contact with recently is the notion that the US defense establishment does not believe that the US commercial establishment builds a billion transistors SoCs, and they work. I put "establishmen...
- 12 Apr 2022
Verification: Device Training for High Speed DRAMs

Shyam Sharma

As the device frequencies and the data rates go up with every new generation of Interface and memory devices, sampling of the signals and the transferring of the data b/w Initiator and target is being increasingly difficult with ever shrinking data eyes.  

To assist with handshaking for the high speed I/O, most of the newer generation of the interfaces and memories support an ever-increasing number of Training Modes that…
- 12 Apr 2022
Breakfast Bytes: The Convergence of Photonic and Electronic ICs

Paul McLellan

At the recent DesignCon in Santa Clara, one of the keynotes was by John Bowers of UC Santa Barbara. I'll start with his summary from his last slide: There is a silicon photonics revolution happening. The challenge is that silicon is a terrible...
- 11 Apr 2022
Spotlight Taiwan: Cadence Perspec驗證在異質多核心行動處理器之應用

candyyu

作者:Vic Chen, Principal Application Engineer, Cadence可攜式測試與刺激標準(Portable Test and Stimulus Standard, PSS）是現今業界採用於晶片前期功能測試的抽象驗證過程中，同時也能正確地重新定義驗證的一套標準。它可謂是自Verilog和VHDL以來最重要的標準協議了。我們已經習慣一種基於非常不穩定的基礎架構的驗證方法，但此方法較重視刺激而不是檢測，且會基於檢測報告來做為驗證工作的結束，而不是根據驗證意...
- 11 Apr 2022
Breakfast Bytes: Sunday Brunch Video for 10th April 2022

Paul McLellan

https://youtu.be/fmV1XVY-ZiI Made at Coyote Hills Regional Park (camera Carey) Monday: Intelligent System Analog Design Tuesday: Jack Dongarra Receives Turing Award Wednesday: Sam Zeloof: Who Needs a Cleanroom When You Have a Garage? Thursd...
- 10 Apr 2022
System, PCB, & Package Design : BoardSurfers: Reasons to Move to 17.4-2019 HotFix SPB17.40.028 of Allegro PCB Editor

Monika

The HotFix SPB17.40.028 of 17.4-2019 of Allegro® PCB Editor has been rolled out and is now available for download. This release includes various enhancements, new features, and product changes that address design challenges and speed up the ...
- 8 Apr 2022
Breakfast Bytes: Ericsson Cellular Network at TÜV Rheinland Test Center

Paul McLellan

At the end of March, I went to the TÜV Rheinland Test Center. TÜV stands for Technischer Überwachungsverein, which is Technical Inspection Association in English. There are three big ones. TÜV Nord, TÜV Rh...
- 8 Apr 2022
Breakfast Bytes: Identity Is the New Perimeter

Paul McLellan

On March 10th, Black Hat organized a webinar called Identity is the New Perimeter. If you know anything about security then you might guess that this webinar is going to be about zero-trust. The first presenter was Charl van der Walt from t...
- 7 Apr 2022
Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 13: Analog Fault Simulation

Parula

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. That's why we're happy to show you how to perform analog fault simulation using the Fault Simulation run mode in Virtuoso ADE Assembler.
- 7 Apr 2022
PCB設計／ICパッケージ設計: 2022年3月リリース、Cadence OrCAD / Allegro17.4-2019 HotFix SPB17.40.028の新機能ハイライト

SPB Japan

OrCAD® および Allegro®のHotFix 028 (QIR 4, アプリケーションのスプラッシュ画面では “2022” と表示されます) の更新プログラムが Cadence Downloads にリリースされました。このブログ記事では、この更新プログラムにアクセスするための重要なリンクと、主要な機能変更や新機能についての概要をご紹介します。 OrCAD/Allegro 17.4 (SPB174) 以下は主要な機能変更や新機能のリストとその...
- 6 Apr 2022
Breakfast Bytes: Sam Zeloof: Who Needs a Cleanroom When You Have a Garage?

Paul McLellan

At the end of last year, I was mindlessly looking at YouTube when their "algorithm" decided that I should watch a video made by a guy named Sam Zeloof. He was literally building integrated circuits in his garage using cobbled-together or ob...
- 6 Apr 2022
Computational Fluid Dynamics: Replicating da Vinci’s Aerial Vehicle Design

Veena Parthan

The increasing value of the drone industry is pushing the limits of evaluating and improving the aerodynamics of UAVs for enhanced range and extreme maneuvers.
- 6 Apr 2022
Computational Fluid Dynamics: Rank-N Nonlinear Harmonic Method Unlocks More Precise And Reliable Turbomachinery Designs

AnneMarie CFD

The NLH Rank-n feature unlocks the possibility of simulating unsteady phenomena across a limitless number of turbomachinery rows: engineers can now benefit from more realistic flow assessments, leading to more precise and reliable designs.
- 5 Apr 2022
Breakfast Bytes: Jack Dongarra Receives Turing Award

Paul McLellan

Last week, the ACM announced that Jack Dongarra was being honored with the 2021 Turing Award, considered to be the equivalent of the Nobel Prize for Computer Science, and comes with the same million dollars. His name might not be that familiar, but t...
- 5 Apr 2022
SoC and IP: TWS Earbud Design: Scaling up

The Prakashian

We now look to scale the architecture from Good-enough earbuds, to Better (mid-tier) and Best (high-end) models. While adding features and improving user experience, we hope to preserve the software investment made by OEM and/or SoC vendors. This is essential for fast time-to-market, as we reach to grab a larger portion of the available market TAM.
- 4 Apr 2022
SoC and IP: TWS Earbud Design Is About Scaling

The Prakashian

It is important that OEMs and SoC providers of TWS earbuds prepare to offer the quality and features the market expects of next generation products. Here, we explore the architecture of the signal path and the approach to scaling it across different product tiers.
- 4 Apr 2022
Verification: LPDDR5 Verification from PHY to System Level

Vinod Khera

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system’s performance. These performance expectations make the whole system verification extremely challenging and become more complex as the project evolves from IP Level verification to Memory sub-system and System-level as you start integrating the memory pieces in the whole SoC. In this blog, I will be discussing how Cadence helps to overcome…
- 4 Apr 2022
Breakfast Bytes: Intelligent System Analog Design

Paul McLellan

There are many perceptions about analog design that might have been true once. For example, all analog design is done by grey-haired designers with decades of experience wrestling the signals to the ground using just a polygon-based layout editor and...
- 4 Apr 2022
PCB設計／ICパッケージ設計: BoardSurfers: Allegro PCB Editorでの寸法データ入力に関する概要

SPB Japan

プリント基板がより複雑かつ軽量になっていく中、費用対効果が高く信頼性の高い基板の設計・製造は、これまで以上に重要となっています。デザインの詳細情報が不正確／不完全では、アセンブリの工程で基板の製造に影響を与える可能性があります。PCBデザインに寸法データ(ディメンジョン)を追加することにより、そのPCBデータが製造用に出力されたときにすべてがぴったり合うようデザインに関する十分な詳細情報を提供できます。なぜ寸法データが必要なのか？ PCBに寸法データを付加する主な目的は、重要な穴の位置、PCB...
- 3 Apr 2022
Computational Fluid Dynamics: Combining Structured and Unstructured Meshes: The Holy Grail for CFD Engineers

AnneMarie CFD

Flow solvers must be able to read the type of meshes behind them, and as most flow solvers only accept either structured or unstructured meshes, this is can be a no-win situation. However, within Cadence's Omnis™︎ environment, users can switch between meshing approaches in a single click.
- 1 Apr 2022
Breakfast Bytes: The All-Purpose EDA Keynote

Paul McLellan

Today, it is April 1st and so it is tempting to do some spoof post, but most of those are lame. Plus, it is hard to surpass the BBC's 1957 news item about the spaghetti harvest. This fooled so many people since it was decades before the era when ...
- 1 Apr 2022

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