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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

The Importance of Ecosystems in the Internet of Things Era

As we develop electronics in early 2014, the battle between processor architectures…

• 4 min read
ARM ecosystem , System Design and Verification , electronics design , Internet of Things , ARM , embedded systems

Analog/Custom Design

Fast Yield Analysis and Statistical Corners

The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random…

• 3 min read
ADE GXL , ADE XL , fast yield analysis , Virtuoso Analog Design Environment , Monte Carlo , statistical corners

Verification

Randomizing Error Locations in a 2D Array

A design team at a customer of mine started out with Specman for the first time…

• 3 min read
AF , IntelliGen , Specman , e code , stimuli , Generation , Funcional Verification

SoC and IP

RealTek Shows New HiFi-based Codec with Software from Sensory and ForteMedia

Watch these demonstrations of RealTek's new ALC5677 audio codec - which uses HiFi…

• less than a min read
voice recognition , audio , Sensory , microphone , HiFi , Tensilica , ForteMedia , always-on , RealTek

Analog/Custom Design

Virtuosity: 14 Things I Learned in January and February 2014 by Browsing Cadence…

Time just got away from me last month, so here's two months worth of new content…

• 2 min read
AMS , Corners , ADE , ADE-GXL , PVT corners , Custom IC Design , Virtuoso Layout Suite

System, PCB, & Package Design 

Customize Your Menus Dynamically with SKILL in Cadence Allegro 16.6-Based Layout…

Many users of the Allegro, APD, and SiP tools are familiar with the great flexibility…

• 5 min read
IC Packaging and SiP Design , IC packaging SiP Layout , Digital SiP design , IC Packaging & SiP design , IC packaging documentation , IC Package Physical layout and co-design

Whiteboard Wednesdays

Whiteboard Wednesdays—How 2D Solutions Help Close the Memory Wall Gap

In this week's Whiteboard Wednesdays episode, Scott Jacobson deep dives into 2D memory…

• less than a min read
performance , Whiteboard Wednesdays , 2D Memory , DDR4 , UFS , eMMC , power

SoC and IP

MIPI Protocols—Making Mobile Happen at MWC

MIPI protocols are expected to ship in over 4 billion mobile devices this year. That…

• less than a min read
controller IP , Verification IP , Design IP , IP , MIPI Alliance , PHY , BIF , Slimbus , VIP , MIPI , CSI , MWC , semiconductor IP , M-PHY

SoC and IP

Android Audio Offload Explained at Mobile World Congress

Want to lower power in your next Android TM device? Look to the industry's first…

• less than a min read

Verification

New Incisive Verification App and Papers at DVCon by Marvell and TI

If you're an avid reader of Cadence press releases (and what self-respecting verification…

• 1 min read
Formal Analysis , formal , Funcional Verification , DVCon 2014 , Formal verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About DEHDL’s Cross Referencing of Hierarchical Nets? 16.6 has Several…

The 16.6 Design Entry HDL (DEHDL) Cross Referencer has some new enhancements to report…

• less than a min read
PCB , Cadence Design Systems , hierarchy , cadence , 16.6 , hierarchical schematics , SPB , Design Entry HDL , design , Design Entry , Grzenia , ConceptHDL , hierarchical block

Verification

Incisive vManager at DVCon - Come See It!

Have you heard the news? There is a new version of vManager announced this week,…

• 1 min read
collaboration , : Functional Verification , Verification methodology , cadence , Functional Verification , vPlan , Verisity , DVcon , metric-driven verification , functional coverage , vManager

Whiteboard Wednesdays

Whiteboard Wednesdays - How the MIPI Alliance Works to Enhance Mobile Devices

In this week's Whiteboard Wednesdays episode, Moshik Ruben, Product Marketing Director…

• less than a min read
mobile devices , UniPro , D-PHY , MIPI , MIPI protocols , M-PHY

Analog/Custom Design

What's the Worst that Could Happen?: Worst-Case Corners in ADE GXL

In addition to combinations of temperature range and power supply voltages (usually…

• 2 min read
Variability Aware Design , Corners analysis , worst case corners , Virtuoso Analog Design Environment , ADE-GXL , Analog Design Environment

Whiteboard Wednesdays

Whiteboard Wednesdays - Implementing Always-On Audio

In this week’s Whiteboard Wednesdays episode, Gerard Andrews, from the Tensilica…

• less than a min read
mobile devices , Whiteboard Wednesdays , IP , sensor fusion , voice trigger , Tensilica , HiFi DSP , always on audio , audio playback

Analog/Custom Design

What Your Circuit Doesn't Know, Can Kill It!

Device variation has been a long-standing problem in custom design. Over the years…

• 1 min read
IP , post-extraction , corner , in-design , Virtuoso Analog Design Environment , physical implementation , device variation , IC design

System, PCB, & Package Design 

Improve Design Quality with Adjacent Layer Object Avoidance in the 16.6 Cadence APD…

In this week's discussion, let's take a look at a cornerstone of every good substrate…

• 2 min read
IC Packaging and SiP Design , package , packaging , IC Packaging and SiP , APD , IC Packaging & SiP design , SiP Layout , IC Package Physical layout and co-design

Verification

e Language Editing with Emacs

Specman and e have been around for a while, and some clever people have developed…

• 1 min read
AF , Specman , Incisive Debug Analyzer , e code , xemacs , Funcional Verification , editing , emacs

Whiteboard Wednesdays

Whiteboard Wednesdays - What is VIP?

Today, our continuing Whiteboard Wednesdays video blog series will provide an overview…

• less than a min read
Verification IP , Memory , VIP , EDA , interfaces , SoC design
CDNS - Fix Layout Hompage