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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Chipworks Looks at Smartphones

Chipworks buys hundreds of devices every year and strips them down to look at the…

• 4 min read
Intel , Apple , Samsung , TSMC , Linley , wearables , mobile , GlobalFoundries , smartphones , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Using Processor Clusters to Implement Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen describes how to use processor…

• less than a min read
Whiteboard Wednesdays , IP , processor clusters , Tensilica , neural networks , CNN

SoC and IP

Fastest Octal SPI Flash Interface Available Now From Cadence

Flash memory is being utilized in computers and electronic devices found in Automotive…

• 1 min read
PHY , octal spi , spi , nor flash

SoC and IP

Cadence at Flash Memory Summit 2016: Octal SPI, eMMC 5.1, ONFi 4, and Tensilica SSD…

If you design with flash memory components or IP solutions, head on over to the Santa…

• 1 min read
Verification IP , Design IP , Memory , VIP , Tensilica , semiconductor IP , Design and Verification IP , Design IP and Verification IP , memories

Breakfast Bytes

Smartphones: Linley's Annual Review

Last week was the Linley Mobile Conference, although it is now the Mobile and Wearables…

• 3 min read
Apple , Samsung , wearables , mobile , Smartphone , Huawei

Analog/Custom Design

Virtuoso Variation Option: Reliable High-Yield Design with Scaled-Sigma Sampling

What’s Scaled-Sigma Sampling? Scaled-sigma sampling (SSS) is an efficient algorithm…

• 4 min read
Variability Aware Design , scaled sigma sampling , ADE , IEEE , Variation , yield

Analog/Custom Design

Analog Design Resonance: Quick and Efficient Regression Scripts–Now Possible with…

The new Virtuoso ADE product suite is packaged with a lot of easy-to-use, productivity…

• 3 min read
ADE Explorer , ADE , Custom IC Design , ADE Assembler

Breakfast Bytes

CDNLive Boston Preview

The full agenda for CDNLive Boston is now available. This is really "East Coast"…

• 2 min read
CDNLive , Power Integrity , cdnlive boston , Boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

Nokia's Rise and Fall...and Maybe Rise Again

If you live in the US, then it is hard to believe how dominant Nokia was in mobile…

• 7 min read
microsoft , nokia , elop , mobile , Breakfast Bytes , iPhone

System, PCB, & Package Design 

What's Good About ADW’s Model Management? 16.6 Has a Few New Enhancements!

New Model Management capabilities are now available in the SPB 16.6 Allegro Design…

• less than a min read
Allegro 16.6 , flow manager , 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , setup , design data management , design , PCB design , Grzenia , model editor , library , ADW , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Smart Layer Behavior for Add Connect? It’s in…

When using the Add Connect command in the 16.6 Allegro PCB Editor , the active layer…

• less than a min read
PCB , Allegro 16.6 , layer stacks , PCB Editor , Layout , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Two-Layer PCB Support? Check Out 16.6!

By default, the top and bottom stackup layers do not support the placement of embedded…

• 2 min read
Allegro 16.6 , layer stacks , via , PCB design , Grzenia , Allegro PCB Editor , Allegro

Analog/Custom Design

Adding Weighted Noise Via Calculator Custom Function

Applying a weighting factor to a Noise Summary run requires lots of steps and the…

• 1 min read
Analog Design Environment , ADE XL , ADE , ViVA , Custom IC Design

Analog/Custom Design

Virtuoso Video Diary: Getting Started with the New Virtuoso ADE Product Suite

Hey, did you hear the buzz around the new Virtuoso ADE product suite , which was…

• 3 min read
Analog Design Environment , Virtuoso ADE Verifier , ADE GXL , Analog Simulation , ADE XL , ADE , Block-level simulation , Monte Carlo , Virtuoso , ADE-GXL , ADE-XL , Virtuoso Video Diary , Custom IC Design , Virtuoso ADE Explorer , Virtuoso ADE Assembler

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Advanced Flex and Rigid-Flex Design Support (Reason…

Why Rigid-Flex? For nearly all applications, customers continue to demand smaller…

• 4 min read
Allegro 17.2 , Rigid-Flex , MCAD-ECAD , PCB design , Allegro PCB Editor , IPC-2581 , Why Move Up to 17.2

Breakfast Bytes

IEDM, New This Year

It might seem a bit premature to be talking about IEDM since it isn't until December…

• 3 min read
International Electron Devices Meeting , 5nm test chip , IEDM

Breakfast Bytes

Gimme a G...Gimme a 3...Whatcha Got?...DSP

Today at the Linley Mobile and Wearables Conference in Santa Clara, Cadence is announcing…

• 2 min read
linley mobile and wearables , linley group , Fusion G3 , Linley , Tensilica , linley mobile , Tensilica Fusion G3 DSP , Breakfast Bytes

System, PCB, & Package Design 

Cadence Online Support—Empowering Learning! New Learnings—Sigrity 2016

Cadence Online Support Features Setting up ‘My Alerts” The My Alerts section displays…

• 1 min read
PCB SI , Constraint-driven PCB Design flow , PDN , Signal Intregrity , SigXP UI , PCB Signal and power integrity , Power Integrity , "PCB SI" , Signal Integrity , "PCB design" , PCB Signal integrity , Allegro PCB SI , SI analysis and modeling , power

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to the New Tensilica Fusion G3 DSP

In this week's Whiteboard Wednesdays video, Paul Garden provides an introduction…

• less than a min read
DSP , Whiteboard Wednesdays , IP , floating point DSP , Tensilica , Tensilica IP
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