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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Digital Design

CDNLive! Silicon Valley Abstract Deadline Extended 1 Week

The deadline for submitting abstracts to CDNLive! Silicion Valley 2010 has been extended…

• less than a min read
CDNLive!

Verification

System Realization Webinars Start Sept 8th

Starting September 8th Cadence will be hosting a series of webinars about various…

• 2 min read
TLM , webinars , system realization , Calypto , Imperas , CircuitSutra , XtremeEDA , ESL

SoC and IP

OCZ accentuates the positive (SSDs) and eliminates the negative (low-margin DRAM…

PC add-on vendor OCZ has announced today that its future is in SSDs and high-speed…

• 1 min read

Verification

Performance Tips and Tricks: Another Specman Performance Series

Building on the great success of Efrat Shneydor's previous blog series, Performance…

• 1 min read
performance , Specman , Functional Verification , Testbench simulation , EDA , e , team specman , Aspect Oriented Programming , AOP

Verification

Report On Chelsio’s DAC Case Study In Formal Verification

As the leader of the Formal Verification R&D team, I'm always fascinated by the many…

• 2 min read
DAC , ABV , verification strategy , Functional Verification , Formal Analysis , formal , Incisive , IFV

SoC and IP

Embedded SSDs: SanDisk’s iSSD puts 64Gbyte SATA SSD on a BGA device measuring only…

The convenience of SSDs that look like HDDs is that they can seamlessly plug and…

• 1 min read

SoC and IP

Steve Wozniak talks about the importance of memory in system design

Last week at the Flash Memory Summit, Steve Wozniak gave a keynote presentation where…

• less than a min read

SoC and IP

SSDs versus HDDs: Comments on that giant, yellow, flashing, caution light

A couple of weeks ago, I noted the continued disparity between SSD and HDD pricing…

• 2 min read

Digital Design

Webinar: SOI Gives More Performance Per Watt, And There's An Easy Path

If you've seen any of the recent buzz lately around Silicon-On-Insulator (SOI),…

• less than a min read
Low Power , webinars , Low-Power , Power-Efficient Design , Digital Implementation , Silicon on Insulator , Power Analysis , mixed signal , SOI , power

SoC and IP

NAND Flash in Space: JPL’s Strauss reports advanced Flash devices with finer geometries…

Yesterday, I blogged about a presentation on embedded SSDs given at the Flash Memory…

• 5 min read

Verification

Inside The Virtual File System

As part of my ongoing effort to report and explain interesting topics related to…

• less than a min read
virtual file system , DS-5 , system , software , Virtual Platforms , ARM

SoC and IP

SSD Form Factors: Viking Modular Solutions talk at Flash Memory Summit explodes the…

Everyone “knows” what an SSD looks like. It looks just like an HDD, usually in a…

• 3 min read

System, PCB, & Package Design 

What's Good About Deleting Parts in ADW? You Can Easily Do This In ADW16.3!

Part, Schematic, Footprint and Models can all be deleted from the database now with…

• 3 min read
SPB16.3 , data management , DEHDL , PTF , DBeditor , Allegro 16.3 , SPB 16.3 , property , Allegro Design Workbench , Library flow , SPB , Design Entry HDL , design , PCB design , Design Entry , ADW 16.3 , Allegro PCB Editor , Librarians , ConceptHDL , library , ADW , Allegro

Analog/Custom Design

Analog Design vs. Automation -- Why Are They At Odds?

Back in 2002 and 2003 there was a lot of talk about analog synthesis being the …

• 2 min read
IC 6.1 , Bleasdale , analog , ADE , Virtuoso Analog Design Environment , optimization , Virtuoso , ADE-GXL , ADE-XL , Parasitic analysis , Circuit Design , Custom IC Design

SoC and IP

Andy Walls of IBM talks about NAND Flash for Enterprise Applications

Just got back from a morning spent at the Flash Memory Summit. The last talk I listened…

• 2 min read

SoC and IP

Intel’s SSD roadmap starts appearing on the Web

Any company in the SSD business knows it must face Intel, so there’s always wide…

• less than a min read

SoC and IP

AgigA Tech DDR3 memory module combines SDRAM and NAND Flash for data backup on one…

AgigA Tech, a memory-module vendor and a subsidiary of Cypress Semiconductor, has…

• 1 min read

Verification

I Think, Therefore I Blog (Cogito Ergo In Araneam Scribo)

I realized that I have just passed the second anniversary of my first blog post…

• 2 min read
uvm , CDNLive , blog

Verification

Ericsson Selects Specman Constrained-Random Verification To Improve Efficiency And…

Sarmad Dahir of Ericsson switched from directed testing to constrained-random test…

• less than a min read
Specman , VIP , Coverage-Driven Verification , EDA , Aspect Oriented Programming , MDV , AOP , IES-XL
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