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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Breakfast Bytes

What's For Breakfast? Video Preview March 5th to March 9th 2018

https://youtu.be/YesJPmKCeio Coming from Embedded World, Nuremberg (camera Robert…

• less than a min read
AMD , IBM , 3nm , red hat , imec , Spectre , Embedded World , linux

Whiteboard Wednesdays

Whiteboard Wednesdays - Unpacking the DFI Low-Power Interface

In this week's Whiteboard Wednesday, John MacLaren describes the operation of the…

• less than a min read
Low Power , Whiteboard Wednesdays , DFI , DDR PHY

Breakfast Bytes

Embedded World 2018: Dreaming of Electric Cars

I am at embedded world in Nuremberg. One thing that is not here is warm weather.…

• 7 min read

SoC and IP

Why Software-Based GPS Is Great for Location-Based IoT Applications

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo…

• 1 min read

Breakfast Bytes

How Many Journalists per Square Acre?

It doesn't matter how low your standard is for science journalism, the journalists…

• 5 min read
kilowatt , degree , kilowatt hour

Analog/Custom Design

Take Advantage of Advancements in Real Number Modeling and Simulation

Verification is the top challenge in mixed-signal design. Bringing analog and digital…

• 2 min read
real number modeling , analog , Mixed-Signal , RNM , mixed-signal verification

Verification

Xcelium and Cavium: What’s the Deal?

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers…

• 1 min read
thunder x2 , video , Cavium , xcelium

Breakfast Bytes

Patents: Licensed by the Ton

I wrote recently about What Happens in a Patent Lawsuit? Today, I want to look at…

• 8 min read
patent , troll , non-practising entity , cross-licensing , npe

SoC and IP

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

• 4 min read
Galileo , GPS , IoT , Tensilica DSPs

Breakfast Bytes

How Do You Get to Be CEO?

I wrote last week about Being CEO and I said that I'd done it twice in my career…

• 6 min read
board , management , chief executive officer , leadership , CEO

Analog/Custom Design

Virtuosity: New Eye Diagram Measurements

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create…

• 2 min read
Eye Mask , Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , ADE XL , ADE , eye diagram , Analog Design Environment , ViVA , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Verification

New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

As discussed in the previous installment of this blog, a new class of atomic transactions…

• 1 min read
amba5 , ACE5 , AXI5 , Atomic Transactions

Breakfast Bytes

What's For Breakfast? Video Preview February 26th to March 2nd 2018

https://youtu.be/wq86edcqTdw Coming from Building 10 lobby (camera Sean) Monday…

• less than a min read
fec , patent , journalism , Embedded World , forward error correction

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)

Backchannel Training Another capability related to equalization adaptation is backchannel…

• 2 min read
Serial link analysis , IBIS-AMI , PCIe , Signal Integrity , Backchannel , Sigrity

Breakfast Bytes

Paul Kocher: Differential Power Analysis and Spectre

Paul Kocher is a legend in security. A couple of weeks ago SiFive hosted a seminar…

• 11 min read
security , risc-v , Spectre , Paul Kocher , sifive

Digital Design

Wind of Change in Hardware Design

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I…

• 2 min read
High-Level Synthesis , deep learning , machine learning , Stratus , HLS

Breakfast Bytes

Is Big Brother Watching You?

I recently came across a fascinating piece by Paramal Satyal . He is Nepalese although…

• 6 min read
security , cookie , webbkoll , advertising

Verification

Coming to DVCon? It's Not Too Late to Sign Up!

Are you coming to DVCon this year? It’s right around the corner, but it’s not too…

• 1 min read
Functional Verification , DVcon 2018 , tutorials , event

Whiteboard Wednesdays

Whiteboard Wednesdays - Using DDR PHY Power Features to Reduce Power Dissipation

In this week's Whiteboard Wednesday video, Marc Greenberg explains the ways to optimize…

• less than a min read
Whiteboard Wednesdays , DDR PHY , Low Power DDR
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