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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

The Internet of Space

At EDPS back in May (yes, I know I'm behind), Andrew Filo talked about Building the…

• 3 min read
kicksat-2 , EDPS , femto-satellite , space , NASA , internet of space , Breakfast Bytes

Verification

Creating Code from Tables

Some things are best described with tables—each column shows the values for one category…

• 6 min read
Specman , Tables , e , verification

Breakfast Bytes

Protium: FPGA Prototyping the Cadence Way

I attended a recent workshop on Protium titled Accelerating Embedded Software Development…

• 4 min read
TTP , Protium , FPGA prototyping , time to prototype , Breakfast Bytes , FPGA , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Bluetooth 5: Making Mobile Connectivity Seamless in an IoT…

Tired of struggling with pairing your Bluetooth devices and getting them to work…

• less than a min read
Whiteboard Wednesdays , IoT , range limitations , bluetooth , Internet of Things , mobile , Bluetooth 5 , connectivity

Breakfast Bytes

Portable Stimulus Standard

There is an Accellera working group that is developing a portable stimulus standard…

• 7 min read
54dac , DVcon , Accellera , pss , Breakfast Bytes , portable stimulus standard

Breakfast Bytes

IEDM in December—7nm Announcements

Soon it is the International Electron Devices Meeting. It takes place in San Francisco…

• 4 min read
extreme ultra violet , iedm 2016 , IBM , Samsung , TSMC , GlobalFoundries , 7nm , EUV , IEDM

Breakfast Bytes

What's For Breakfast? Video Preview November 28th to December 2nd

https://youtu.be/CUGTiPJQjuI Monday: My preview of IEDM which includes 7nm…

• less than a min read
risc-v , IBM , 7 nanometer , Perspec , Protium , Samsung , TSMC , gf , risc-v workshop , iOS , FPGA prototyping , femto-satellite , GlobalFoundries , pss , internet of space , IEDM , portable stimulus standard

Breakfast Bytes

Happy Thanksgiving. Do You Have Toenailitis?

It’s Thanksgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

• 3 min read
bayes' theorem , physicians' knowledge of statistics , statistical literacy , false positive , false negative , turkey , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: ADE Explorer Setup - Save Now and Reuse Later!

Have you ever come across a situation where you have a test setup in ADE Explorer…

• 3 min read
Explorer , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , Virtuoso Video Diary , mixed signal

System, PCB, & Package Design 

Learning Advanced Flex and Rigid-Flex Design Support in Allegro 17.2-2016

Allegro PCB Editor now offers Rigid-Flex applications where it’s common to have different…

• 2 min read
Cadence Design Systems , PCB Editor , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

Future of EDA: The Q & A

There was a recent panel discussion at Cadence on the future of EDA. The panelists…

• 4 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Breakfast Bytes

Future of EDA: Industry...Well, Cadence...Weighs In

There was a recent panel discussion at Cadence on the future of EDA. If you didn…

• 3 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Breakfast Bytes

The Future of EDA: The View from Academia

There was a recent panel discussion at Cadence on the future of EDA. Of course the…

• 6 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Verification

A Personal History of Functional Verification

In my most recent blog post , I summarized some of the key points from an October…

• 4 min read
ASIC , uvm , pswg , formal. Verisity , Functional Verification , System Design and Verification , OVM , System Development Suite , constrained-random , Simulation acceleration , Accellera , metric-driven verification , Virtual Platforms , Hardware/software co-verification , simulation , FPGA , System Design and Verification

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Via Structures - The Next Generation High Speed…

Via transitions are very common for signals. And in high speed frequencies, these…

• 2 min read
diff pairs , Signal Intregrity , High Speed , PCB design , differential pairs , SI analysis and modeling , Differential Pair Support , Why Move Up to 17.2

Breakfast Bytes

RISC-V 5th Workshop Preview

The 5th RISC-V workshop is coming up on November 29 and 30 on the Google Quad campus…

• 3 min read
risc-v , risc-v foundation , google , risc-v workshop , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview November 21st to 25th

https://youtu.be/dHvlzjjH9SA Monday: The Academic Panel: the Academics Go First…

• less than a min read
Alberto , thanksgiving , Cadence Academic Network , academia , Stanford , cal , industry , UC Berkeley

Breakfast Bytes

JasperGold: Thoroughbred Performance

At the largest gathering of formal verification (FV) engineers in the world, also…

• 6 min read
JUG , formal , Visualize , Jasper , jaspergold apps , JasperGold , Breakfast Bytes , verification

System, PCB, & Package Design 

Why SerDes Signaling Is Trending Towards PAM Encoded Signals

What’s the difference between NRZ, PAM-3 and PAM-4? Here are three graphs that clearly…

• 2 min read
Serial link analysis , PAM-4 , Sigrity , PAM-3
CDNS - Fix Layout Hompage