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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

GLOBALFOUNDRIES' Dual Roadmap

The Story So Far GLOBALFOUNDRIES had a 28nm Hi-K PolySi process. I think that…

• 5 min read
glofo , 22fdx , 12fdx , 14nm , emram , GlobalFoundries , 7nm , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: Creating Net Groups and Constraining Them with Spacing Using…

In this new age of complex designs and scaling of technology nodes, there are more…

• 4 min read
Advanced Node , Virtuoso Schematic XL , Virtuoso Video Diary , Custom IC Design , VLS XL , Virtuoso Layout Suite XL

Breakfast Bytes

How to Verify MIPI Protocols

At the recent MIPI DevCon, Cadence's Ofir Michaeli gave two presentations on verification…

• 5 min read
Verification IP , layered protocol , VIP , MIPI , mipi devcon , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview October 17th to 21st (video)

https://youtu.be/P3jRt2HEe8U Monday: GLOBALFOUNDRIES announced new nodes on their…

• less than a min read
glofo , Memory , linley processor conference , MemCon , network function virtualization , Cisco , Carnegie Mellon University , Andrzej Strojvas , VMware , Kaufman Award , 12fdx , cmu , network virtualization , pdf solutions , ST Microelectronics , GlobalFoundries , thomas skotnicki , kaufman

Breakfast Bytes

MemCon 2016: Storage Class Memory

MemCon, the annual all-things-memory conference originally started by Denali and…

• 7 min read
vertical flash , SCM , Memory , MemCon , LPDDR , flash , storage class memory , IBM , ddrx , DRAM , DDR , Breakfast Bytes

System, PCB, & Package Design 

What’s Good About Allegro PCB Editor Backdrill Capability? New Capabilities in 17…

The 17.2 Allegro PCB Editor has improved backdrill capabilities. Backdrill data…

• 3 min read
PCB , PCB Layout and routing , Allegro 17.2 , Allegro GUI , layer stacks , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Why Move Up to 17.2 , Allegro

Breakfast Bytes

Cache Coherency Is the New Normal

You hear a lot about cache coherency these days. In fact, at the recent Linley processor…

• 6 min read
linley processor conference , linley group , Arteris , Linley , cache coherent , cache coherency , netspeed , cache , ARM , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Driving Forces and Design Concerns Behind PCI Express Ge…

In this week's Whiteboard Wednesdays video, the second in a two-part series, Lana…

• less than a min read
Whiteboard Wednesdays , PCIe , PCI Express Gen4 , PCI Express

System, PCB, & Package Design 

Welcome to the Signal Integrity and Power Integrity Community

This is your resource for all things regarding Signal Integrity and Power Integrity…

• less than a min read
PCB , SI , PI , IC Package , Power Integrity , Signal Integrity

Academic Network

Ultra-Wide-Band Workshop for Balkan Countries

Countries which were founded after the collapse of Yugoslavia have long tradition…

• 1 min read
Croatia , Cadence Academic Network , academic workshop , Balkan , academia , Virtuoso , university program

Breakfast Bytes

RISC-V: the Case For and Against

At the Linley Processor conference recently, there was a presentation about RISC…

• 7 min read
risc-v , linley processor conference , EEMBC , Linley , Krste Asanović , Breakfast Bytes , markus levy

Breakfast Bytes

DVCon Europe Preview

DVCon Europe in Munich is coming up on 19 and 20 October. For any Americans reading…

• 4 min read
Lanza , NXP , pswg , Perspec , iso26262 , DVcon , Accellera , DVCon Europe , ISO 26262 , portable stimulus , Breakfast Bytes

Verification

The Industry Vision for Portable Stimulus

As I mentioned in my last blog post , portable stimulus is one of the main areas…

• 3 min read
uvm , pswg , Acceleration , Perspec , virtual platform , System Design and Verification , Emulation , System simulation and analysis , Accellera , FPGA prototypes , testbench , portable stimulus , silicon , verification

Breakfast Bytes

Cadence Implementation Flow for an ARM Cortex-A73 at 10nm

Increasingly, taking an appropriate ARM ® processor has become the standard way to…

• 4 min read
cortex-a73 , TSMC , n10 , 10nm , ARM , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview October 10th to 14th (video)

https://youtu.be/Ej7aa83-OFM Monday: A preview of DVCon Europe on 19th/20th October…

• less than a min read
Verification IP , risc-v , Memory , linley processor conference , MemCon , flash , linley group , VIP , MIPI , EEMBC , Arteris , mipi devcon , DRAM , cache-coherency , netspeed , DVcon , DDR , DVCon Europe , sddr , ARM , verification

Breakfast Bytes

Verific: the Name is Short for Verification...But That's Not What They Do

I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific…

• 4 min read
SystemVerilog , parser , IEEE 1801 , Verilog , verific , UPF , VHDL , Breakfast Bytes

Academic Network

Cadence Academic Network in Nordic countries

“Finland is not Scandinavia” was one of the first statements I heard, when I landed…

• 4 min read
Finland , Cadence Academic Network , academia , KTH , Tampere , Norway , TUT , NTNU , Linkoeping , Sweden , university program

Breakfast Bytes

Tensilica Floating Point: Small, Similar Cycles and Lower Power

When I first started programming, the first programming language I learned was Fortran…

• 6 min read
lx7 , DSP , fixed point , fortran , Linley , Tensilica , mathlab , floating point

Whiteboard Wednesdays

Whiteboard Wednesdays - How Much Floating Point Does Your Application Need?

To address the growing needs for floating-point arithmetic in DSP algorithms, all…

• less than a min read
DSP , Whiteboard Wednesdays , IP , Tensilica , floating point
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