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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Vertically Placed Components? It’s in the 16…

The ‘dual_sided_component’ property in the Allegro PCB Editor 16.6 release can be…

• 1 min read
embedded components , interconnects , Allegro 16.6 , PCB design , Allegro PCB Editor

Verification

Dealing with Specman-Simulator Interface Issues—Get Ready to Cook!

Two great documents, aiming to make life easier for a verification engineer, were…

• less than a min read
Specman , debug , Functional Verification , Incisive , e language , simulation

Verification

Time to Play - You Can Now Run Your e Code on EDAplayground

Over the years I've often hoped to have the ability to show someone (a customer,…

• less than a min read
IEEE 1647 , Functional Verification , tech tips , EDA , e language , team specman , Aspect Oriented Programming

SoC and IP

USB Power Delivery Is Better with Type-C

In my previous blog post , I wrote how much better than the existing Type-A and Type…

• 2 min read
USB 3.0 , Design IP , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Verification

Code Coverage at the System Level with Hardware-Assisted Verification (Part II)

In yesterday’s Part I blog post , I talked about a technique for focusing code coverage…

• 4 min read
hardware-assisted verification , code coverage , system-level code coverage , coverage analysis , functional coverage

Analog/Custom Design

Five Reasons I'm Excited About Mixed-Signal Verification in 2015

Key Findings : Many more design teams will be reaching the mixed-signal methodology…

• 7 min read
uvm , mixed signal design , Metric-Driven-Verification , Mixed Signal Verification , MDV-UVM-MS

Whiteboard Wednesdays

Whiteboard Wednesdays—Consumer DRAM Trends

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends…

• less than a min read
Whiteboard Wednesdays , DDR4 , DRAM , DDR3

Whiteboard Wednesdays

Whiteboard Wednesdays—Selecting the Right DDR PHY Solution

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation…

• less than a min read
Whiteboard Wednesdays , IP , Floorplanning , PHY IP , DFI

Analog/Custom Design

Mixing It Up in Hardware (an Advantest Case Study in Faster Full-Chip Simulations…

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test…

• 9 min read
Advantest , Palladium , Mixed Signal Verification , Emulation , mixed signal

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Select by Lasso or Path? 16.6 Has It!

The 16.6 Allegro PCB Editor release contains two new selection options, lasso and…

• 1 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , cadence , Routing , route quality , bulk editing , SPB , PCB Editor , PCB design , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , TripleCheck

System, PCB, & Package Design 

Multi-Fabric Planning for Efficient PCB Design

Recently, an article was published in Printed Circuit Design and Fab about Multi…

• 1 min read
BGA-style package , PCB design , multi-fabric planning , pin assignment

Analog/Custom Design

Virtuosity: A Very Large Number of Things I Learned in September and October 2014…

There has been a flurry of activity on COS over that past couple of months. I can…

• 8 min read
AMS , MMSIM , Advanced Node , ADE XL , Virtuoso , Analog Design Environment , Custom IC Design , Virtuoso Layout Suite XL , IC 6.1.6

Verification

Where Is the Money for IoT?

I attended the Gartner Semiconductor briefing on Oct. 23, 2014, the theme of which…

• 1 min read
Verification IP , DSP , IP , IoT , Tensilica , always-on

System, PCB, & Package Design 

Do You Design Wafer-Level Chip-Scale Packages? Cadence 16.6 SiP Layout Makes Your…

As these types of designs see an increasing number of applications and design starts…

• 4 min read
IC Package , SiP Design , Co-Design , layout pin numbering

Analog/Custom Design

The Elephant in the Room: Mixed-Signal Models

Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these…

• 5 min read
metrics-driven methodology , real number modeling , uvm , CPF , RNM , UPF , mixed signal , MDV , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Verification IP Productivity Tools

In this week's Whiteboard Wednesdays video, Tom Hackett talks about Cadence Verification…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , PureView , productivity , TripleCheck

SoC and IP

Its Name is C, Type-C: The New Superhero of Cables from USB

Isn’t it interesting how, with time, all the nitty-gritty of technology is starting…

• 2 min read
Design IP , IP , Jacek Duda , USB , ip cores , USB3.0

Verification

Generic Dynamic Runtime Operations With e Reflection - Part 3: Additional Capabilities…

This post concludes the series of blog posts that discuss the dynamic capabilities…

• 3 min read
AF , Specman , debug , Functional Verification , Incisive , e language , reflection , simulation
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