Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About Browsing For Power Pins in Capture? It's In SPB16.3!

The SPB16.3 release of Allegro Design Entry CIS (Capture) now allows you to browse…

• 1 min read
"capture CIS" , Capture CIS' , Design Entry CIS , OrCAD Capture , SPB 16.3 , Capture CIS , Capture-CIS , OrCAD , Design Entry , Schematic

SoC and IP

Squeeze bandwidth inefficiencies out of DDR DRAMs in memory subsystem designs

This blog starts with a simple, sad truth: DDR DRAMs are naturally inefficient. If…

• 6 min read

Digital Design

Mixed Signal: Why The Sudden Attention?

With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors…

• 2 min read
DAC , SoC , Mixed-Signal , Digital Implementation , mixed signal

SoC and IP

Why is it so difficult to interface with DRAMs?

One of the maxims in the world of system design is that it has always been relatively…

• 3 min read

Verification

The Future of OVM, VMM, and UVM

In my last blog , I took a look back at the history of how we got to the first delivery…

• 3 min read
SystemVerilog , uvm , methodology , Functional Verification , Open Verification Methodology , OVM , VIP , Accellera , Accellera VIP TSC , VMM

SoC and IP

Google TV and Intel’s CE4100 SOC (Sodaville)--is this a world-beating combo or what…

Having vacuumed up most of the world’s very large and growing Internet advertising…

• 5 min read

SoC and IP

MemCon 2010, July 28: Time to Register. Hundreds already have!

How’s your July shaping up? No, that’s not just an idle question about your future…

• 1 min read

Verification

Tech TIP: Incisive Formal GUI Updates - Making It Easier

The Incisive Formal GUI has had some recent changes made to it. You asked for the…

• less than a min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

SoC and IP

Seagate Tweet unleashes avalanche of speculation: fast gamers' 2.5-inch HDD with…

Earlier this week, Seagate sent out the following Tweet: “Your hard drive is…

• 1 min read

System, PCB, & Package Design 

Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export…

This is the second in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , SiP , Analog and RF SiP design , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , IC Packaging & SiP design , SPB , wirebond profile library , IC Package Physical layout and co-design , Kulicke & Soffa

SoC and IP

LPDDR2: The new mainstream memory for embedded and mobile applications?

Yesterday, ST-Ericsson announced a new smartphone platform called the U8500 which…

• 3 min read

RF Engineering

New Time-Saving Feature in IC6.1.4 ISR2: Plot S-Parameter Data Directly From ViVA…

If you haven't heard about it....there is a new feature in IC6.1.4 ISR2 which makes…

• 2 min read
RFIC , Virtuoso Spectre , Spectre RF , ADE-L , RF designer , MMSIM , Spectre , ViVA , RF design , Circuit Design , harmonic balance , pss

System, PCB, & Package Design 

What's Good About ADW Part Lifecycle? Numerous Improvements in the SPB16.3 Release

The SPB16.3 release of Allegro Design Workbench (ADW) now adds several new key features…

• 1 min read
Allegro Design Workbench , Library flow , Library and design data management , PCB design , ADW 16.3 , Librarians , ADW

SoC and IP

Party on at DAC, says Denali

Back by popular demand, the Denali DAC party. The big one. With the bells and whistles…

• 1 min read

RF Engineering

Using RF Simulation Technology for Analog Applications

The particular nature of analog circuits puts restrictive requirements on circuit…

• 1 min read
RF Simulation , Analog Simulation , RF design , Analog Smart

Verification

UVM World Community Site Now Available!

Yesterday morning, the verification world was buzzing with the first release of the…

• 1 min read
uvm , Verification methodology , Functional Verification , OVM , VIP , Accellera VIP TSC

SoC and IP

1.8-inch SSD with PATA interface targets mini Notebooks, Netbooks, good for embedded…

With all of the recent SSD announcements, you might think that the only form factor…

• less than a min read

Verification

UVM - 10 Years in the Making ...

In case you the missed the news today, the Accellera VIP TSC released the first version…

• 3 min read
SystemVerilog , uvm , Specman , OVM ML , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , vr_ad , OVM SV , e , OVM-e , Accellera , coverage driven verification (CDV) , eRM , Accellera VIP TSC , OVMWorld

SoC and IP

Toshiba stands on 2Xnm NAND platform with devices, SSDs, and hybrid storage

Last week, Toshiba’s president and CEO Norio Sasaki stood firmly upon a leading-edge…

• less than a min read
CDNS - Fix Layout Hompage