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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export…

This is the second in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , SiP , Analog and RF SiP design , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , IC Packaging & SiP design , SPB , wirebond profile library , IC Package Physical layout and co-design , Kulicke & Soffa

SoC and IP

LPDDR2: The new mainstream memory for embedded and mobile applications?

Yesterday, ST-Ericsson announced a new smartphone platform called the U8500 which…

• 3 min read

RF Engineering

New Time-Saving Feature in IC6.1.4 ISR2: Plot S-Parameter Data Directly From ViVA…

If you haven't heard about it....there is a new feature in IC6.1.4 ISR2 which makes…

• 2 min read
RFIC , Virtuoso Spectre , Spectre RF , ADE-L , RF designer , MMSIM , Spectre , ViVA , RF design , Circuit Design , harmonic balance , pss

System, PCB, & Package Design 

What's Good About ADW Part Lifecycle? Numerous Improvements in the SPB16.3 Release

The SPB16.3 release of Allegro Design Workbench (ADW) now adds several new key features…

• 1 min read
Allegro Design Workbench , Library flow , Library and design data management , PCB design , ADW 16.3 , Librarians , ADW

SoC and IP

Party on at DAC, says Denali

Back by popular demand, the Denali DAC party. The big one. With the bells and whistles…

• 1 min read

RF Engineering

Using RF Simulation Technology for Analog Applications

The particular nature of analog circuits puts restrictive requirements on circuit…

• 1 min read
RF Simulation , Analog Simulation , RF design , Analog Smart

Verification

UVM World Community Site Now Available!

Yesterday morning, the verification world was buzzing with the first release of the…

• 1 min read
uvm , Verification methodology , Functional Verification , OVM , VIP , Accellera VIP TSC

SoC and IP

1.8-inch SSD with PATA interface targets mini Notebooks, Netbooks, good for embedded…

With all of the recent SSD announcements, you might think that the only form factor…

• less than a min read

Verification

UVM - 10 Years in the Making ...

In case you the missed the news today, the Accellera VIP TSC released the first version…

• 3 min read
SystemVerilog , uvm , Specman , OVM ML , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , vr_ad , OVM SV , e , OVM-e , Accellera , coverage driven verification (CDV) , eRM , Accellera VIP TSC , OVMWorld

SoC and IP

Toshiba stands on 2Xnm NAND platform with devices, SSDs, and hybrid storage

Last week, Toshiba’s president and CEO Norio Sasaki stood firmly upon a leading-edge…

• less than a min read

Verification

Initial Release of the UVM Now Available!

As Richard Goering just reported , the Accellera VIP Technical Subcommittee (TSC…

• 2 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

System, PCB, & Package Design 

DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

Last year, TimingDesigner improved the interface to PCB SI and many of our joint…

• less than a min read
PCB SI , SI , Signal Intregrity , IBIS , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , "PCB design" , DDR3

SoC and IP

Early Adopter release of UVM now available

Accellera has been working on a new industry-standard verification methodology called…

• 1 min read

Verification

EDA360: Cool People Creating Cool Stuff

Now that we have had some time to reflect on the meaning of EDA360 , it occurred…

• 4 min read
EDA360 , Systemm Design and Verification , OpenStreetMap , Embedded Linux , Embedded Software Engineer

Digital Design

What you didn’t know about DFM for advanced node designs: “In-route” is insuffic…

Recently, there has been a lot of buzz about addressing DFM issues during routing…

• 3 min read
Digital Implementation forums , DRC , design rules , EDA , Encounter Digital Implementation System 9.1 , Manufacturability sign-off , Digital Implementation , Encounter Digital Implementation , EDI system Encounter Digital Implementation System , DFM

SoC and IP

SSDs in embedded control: cold rolling steel in old European factories

By far, most application stories connected with SSDs revolve around servers and PCs…

• 3 min read

SoC and IP

CADENCE TO ACQUIRE DENALI

Complementary Transaction Supports Cadence’s EDA360 Vision SAN JOSE and SUNNYVALE…

• 2 min read

System, PCB, & Package Design 

Economic Recovery on the Way to the Airport

Last week, one of the members of TEAMOrCAD took a trip to China. The ride to the…

• 1 min read
"capture CIS" , PSPICE , "PCB design" , OrCAD , PCB Capture , Schematic

SoC and IP

Mass marketing methods come to SSDs

Newly introduced and available for pre-availability orders, the privately branded…

• 3 min read
CDNS - Fix Layout Hompage