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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Designing DDR3 Interfaces In a Constraint Driven Design Environment

If you’ve been wondering how to capture high speed memory interface design intent…

• less than a min read
SPB 16.2 , PCB Signal and power integrity , Constraint Manager , DDR3

Verification

OVM Now Includes SystemC and e Language Interoperability

More of our customers are using Incisive for transaction level modeling (TLM) and…

• less than a min read
virtual platform , System Design and Verification , OVM , SystemC , prototype

Verification

Reflections on ESL: Where Are We and Where We Are Going

Many of the messages published by Gabe Moretti in his recent EETimes article resonate…

• 1 min read
TLM , RTL , System Design and Verification , EETimes , C-to-Silicon , SystemC , ESL

Verification

OVM e Open Source - It's Official!

Specmaniacs and other e RM & OVM users, Today we offically released the e RM 3.0…

• less than a min read
IEEE 1647 , OVM , OVM e , e , eRM

Verification

DVCon '09 Preview

For those of you that will not be able to make it in person: So you can follow the…

• 2 min read
funtional verification , Functional Verification , VIP , Mike Stellfox , DVcon , Levent Caglar , Jason Andrews

Digital Design

Turning the Downturn Upside Down

Many bemoan the gloom and doom of the present economic situation, and it is true…

• 1 min read
Low Power , OVM , MIPI , encounter , Virtuoso , Spectre , Digital Implementation , Chi-Ping

Verification

Tech Tip: Viewing The Combined Help for IES-XL

IES-XL is comprised of IUS, Incisive Verification Kits with Methodology, Specman…

• 1 min read
Specman , Functional Verification , tech tips , Enterprise Manager , help , IES-XL

Verification

Tips for Opening Cadence Help

[Welecome back the Tech Pubs team as guest bloggers] Sometimes you just need a little…

• 1 min read
Specman , Tech Pubs , Enterprise Manager , Enterprise Planner , Incisive Enterprise Simulator (IES) , IES , IES-XL

Verification

Emulation vs. FPGA Prototyping

There is a continuous debate about FPGA prototyping vs. emulation. This debate is…

• 1 min read
ASIC , prototyping , RTL , System Design and Verification , Palladium , FPGA

Verification

Grey-Boxed Data-Path Approach Using 'when sub-typing'

[Please join Team Specman in welcoming the first guest blogger from our user base…

• 10 min read
when sub-typing , Specman , verification strategy , Functional Verification , Coverage-Driven Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

SoC and IP

Denali MemCon 2009 Website Launched

Denali MemCon Silicon Valley Coming June 22-25; Register now! Denali has just…

• 1 min read

Digital Design

Constraint Construction: What's Its Function? Part 2 of 4

Part 2 - I/O TIMING: Talking Outside The Box It wouldn't be a chip or block if it…

• 3 min read
Constraint Design , STA , Encounter Digital Implementation , Encounter Timing System

Verification

Adaptive Chips Selects OVM Over VMM -- An Interview With Amjad Qureshi

On February 11 Cadence announced that Adaptive Chips had adopted the Incisive verification…

• 2 min read
Adaptive Chips , SystemVerilog , Functional Verification , OVM , VIP , CDV , e , eRM

Analog/Custom Design

Video Demo: Spice 2.0 - The ABCs of APS

Designers have had ubiquitous access to powerful SMP/multicore systems for years…

• less than a min read
APS , SMP , Spice 2.0 , multicore , Custom IC Design

System, PCB, & Package Design 

What's Good About FPGA Capabilities in Capture? Download the SPB16.2 Release and…

With the SPB16.2 release, a few new FPGA enhancements have been added. In recent…

• 1 min read
SPB 16.2 , PCB design , UCF , xilinx , Allegro , FPGA: PCB

Verification

How to Save OS Boot Time In Your SystemC Virtual Platform With Save and Restore

One advantage of using a virtual platform or virtual prototype over real hardware…

• 2 min read
open virtual platforms , virtual platform , System Design and Verification , QEMU virtual platform , Incisive , SystemC analysis , System simulation and analysis , George Frazier , SystemC , Hardware/software co-verification , QEMU

Verification

OVM Is The Safest Bet By 2:1

One of the questions verification engineers will be asking as they head to DVCon…

• 1 min read
SystemVerilog , OVM , VIP , e , DVcon , eRM

Verification

The Real Story on HLS With ANSI-C/C++ vs. SystemC

There's a new post worth reading for anyone interested i n the current state of…

• 3 min read

Verification

SystemC TLM2 based Virtual Prototype Demo at DVCon

DVCon 2009 promises much news about System level design and verification. With Open…

• less than a min read
co-verification engineer , virtualization , Co-verification link , virtual platform , System Design and Verification , embedded software , Incisive , virual platform , system validation/verification engineer , virtual protoype , System simulation and analysis , Coverage Driven Verification for Embedded Software , embedded SW engineer , Incisive Software Extensions , ISX , Hardware/software co-verification , Jason Andrews , ESL , architect , QEMU
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