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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays—SSD Controllers with Tensilica Processors

In this week's Whiteboard Wednesdays video, Neil Robinson follows up on last week…

• less than a min read
Whiteboard Wednesdays , IP , Neil Robinson , Tensilica , SSD controllers

Breakfast Bytes

Embedded Neural Network Summit—How to Build a Silicon Brain

On February 9, Cadence is hosting an all-day Embedded Neural Network Summit., with…

• 2 min read
deep learning , enns , Tensilica , convolutional neural networks , embedded neural networks , Breakfast Bytes

SoC and IP

New 16Gbps Multi-link, Multi-protocol SerDes PHY Enhances Datacenter Connectivit…

PCIe Gen4 is bringing new possibilities to servers and virtualization. The interface…

• 1 min read
PCIe Gen4 , pcie4 , 16Gbps PHY IP , SerDes , SerDes IP

Breakfast Bytes

16Gbps SerDes Multiprotocol Multilink PHY IP

In any advanced node, one of the most important pieces of IP is a high-performance…

• 4 min read
USB 3.0 , pcie4 , 10G-KR , USB , pcie3 , pcie2 , PCIe , 16 Gbps , SerDes , USB 3.1 , SATA , sata3 , Breakfast Bytes

System, PCB, & Package Design 

Customize the Organization of Bond Wires in Your Artwork Films with SiP Layout and…

When it comes to IC Package substrates, Gerber is still one of the most common, most…

• 4 min read
SiP , Allegro package design , Digital SiP design , IC package design , APD , package design , manufacturing , wirebonding , substrate design tools

Breakfast Bytes

Mobile Unleashed: a New Book About ARM

Mobile Unleashed is subtitled The Origin and Evolution of ARM Processors in Our Devices…

• 3 min read
mobile unleashed , mobile , ARM , arm history , Breakfast Bytes

Breakfast Bytes

What Happens in Vegas...May Be in Your Next Chip

Cadence was at CES last week showing the most recent additions to their vision, audio…

• 2 min read
USB Type-C , Consumer Electronics Show , CES , CES 2016 , Tensilica , HiFi DSP , audio weaver , ARM , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—SSD Controller Basics and Trends

In this week's Whiteboard Wednesdays video, Neil Robinson talks about SSD controllers…

• less than a min read
Whiteboard Wednesdays , IP , Neil Robinson , Tensilica , SSD controllers

Breakfast Bytes

Cars, Drones, 8K, and VR/AR—Consumer Electronics Show 2016

CES is held in January each year. It is the largest conference in Las Vegas, which…

• 6 min read
USB Type-C , Consumer Electronics Show , CES 2016 , las vegas , virtual reality , drones , Tensilica IP , autonomous vehicles , augmented reality , Breakfast Bytes

SoC and IP

The Future of High-Speed SerDes

David Axelrad, product marketing manager, SerDes IP, presents Cadence's position…

• less than a min read
PCIe Gen4 , pcie4 , SerDes , gsa

Breakfast Bytes

Tempus Has Over 200 Tapeouts Within 2 Years of Rollout

One of the challenges with any new tool is to drive adoption. There really is a …

• 3 min read
PBA , Tempus , adoption , path-based analysis , tapeout

Breakfast Bytes

Samsung CES Keynote: In Sync with Real Life

Yesterday it was Samsung's turn for a keynote at CES. Depending on exactly how you…

• 4 min read
microsoft , IoT , CES 2016 , Samsung , Corning , BMW

Breakfast Bytes

Drones in the Mini-Forest: Intel's Keynote at CES

Intel's CEO, Brian Krzanich, gave the opening keynote to CES on Tuesday night in…

• 4 min read
Intel , CES , Curie , Realsense , Internet of Things , Breakfast Bytes , Brian Krzanich

SoC and IP

Chris Rowen is Now an IEEE Fellow

For he's a jolly good Fellow, for he's a jolly good Fellow... Effective January…

• less than a min read
Chris Rowen , IEEE Fellow , Tensilica

Breakfast Bytes

Moore's Law at 50: Are We Planning for Retirement?

There has been lots of speculation, especially this year with the 50th anniversary…

• 5 min read
greg yeric , moore's law , ARM , IEDM

Whiteboard Wednesdays

Whiteboard Wednesdays—The Latest on the MIPI CSI-2 2.0 Protocol

In this week's Whiteboard Wednesdays video, Moshik Ruben takes a closer look at the…

• less than a min read
Automotive , CSI-2 , Low Power , Whiteboard Wednesdays , IoT , MIPI protocols , Internet of Things , bandwidth , machine vision

System, PCB, & Package Design 

What's Good About FSP’s Enhanced Multi-Device Connections? 16.6 Has Several New …

The FPGA System Planner (FSP) 16.6-2015 release now provides support for multiple…

• 1 min read
PCB , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , SPB , Grzenia , FPGA

Analog/Custom Design

Virtuosity: Things I Learned in October, November, and December 2015 by Reading Cadence…

I won't even attempt to number the items this time, and I'll have to skip the individual…

• 8 min read
EAD , Rapid Adoption Kit , ADE XL , VLS , RF design , Custom Layout , assertions , IC6.1.7 , Custom IC Design

Breakfast Bytes

Infrastructure: Connecting Mobile to the Cloud

Yesterday's blog post was about the mobile market. But, increasingly, mobile is not…

• 4 min read
computing , cloud-ran , c-ran , storage , infastructure , networking
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