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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Breakfast Bytes

System in Package, Why Now? Part 2

This post is a continuation of last week's post Multiple Die in Packages. Why Now…

• 6 min read
3DIC , more than Moore , moore's law

Analog/Custom Design

Virtuoso IC6.1.8 ISR8 and ICADVM18.1 ISR8 Now Available

The IC6.1.8 ISR8 and ICADVM18.1 ISR8 production releases are now available for download…

• 2 min read
Cadence blogs , ICADVM18.1 , ADE Explorer , IC Release Announcement blog , Virtuoso RF , Virtuoso Custom Placer , Electromagnetic analysis , Virtuoso , CLE , IC Release Blog , Custom IC Design , Virtuoso Layout Suite , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL , clarity

System, PCB, & Package Design 

IC Packagers: Copy and Paste Refresh in 17.4

The most common operations in any tool are probably adding, moving, deleting… plus…

• 3 min read
allegro 17.4 , APD , Allegro Package Designer , Allegro

Breakfast Bytes

Cadence at CES 2020: Tensilica Everywhere

Once again, Cadence will be at CES in Las Vegas. It takes place January 7 to 10,…

• 4 min read
CES , Tensilica

Analog/Custom Design

Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part IV

This is the fourth blog in the multi-part series that aims at providing in-depth…

• 11 min read
AXIEM , SiP , ICADVM18.1 , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF , Package Design in Virtuoso , Electromagnetic analysis , RF design , method of moments , Finite Element Method , Layout Editing , Allegro , clarity

Breakfast Bytes

Xcelium Is 50% Faster on AWS's New Arm Server Chip

At Re:invent, Amazon AWS announced Graviton 2, their second-generation Arm server…

• 3 min read
annapurna labs , nitro , cloud , aws , graviton 2 , cadence cloud , neoverse , ARM

定制IC芯片设计

Virtuosity: 针对高阶工艺节点器件级布线的工具— 干线-干线网状布线工具

本博客强调了干线-干线网状布线功能的重要性，它不仅为定制器件级的布线提供了解决方法，还提高了版图设计师们的工作效率.

• less than a min read
trunk mesh routing , Trunk generation , Interactive Routing , Chinese blog , Pin to Trunk , Cadence blogs , structured routing , ICADVM18.1 , Virtuoso Space-based Router , mesh routing , Layout EXL , trunk-to-trunk mesh , Layout Suite , trunk creation , Generate Trunk , mixed signal , Finish Trunk , EM Trunk Optimization , Custom IC Design , Virtuoso Layout Suite , Custom IC

Verification

Cashing the PSS Promises

A little bit of everything in the blog today: PSS is All Over As someone that was…

• 1 min read
uvm , CDNLive , Acceleration , virtual prototypes , Perspec , perspec system verifier , Emulation , DVcon , Accellera , System Design & Verification , pss , portable stimulus , verification

Breakfast Bytes

Sunday Brunch Video for 8th December 2019

https://youtu.be/3gP0Z02MVps Made at Salinas River State Park (camera Carey Guo…

• less than a min read
sunday brunch

Breakfast Bytes

System in Package, Why Now?

At HOT CHIPS this summer, one of the things I noticed was just how many of the designs…

• 6 min read
chiplet , 3DIC , more than Moore , moore's law

Digital Design

Library Characterization Tidbits: Creating Statistical Libraries for Standard Cells…

Let’s read how you can use the Liberate Variety statistical characterization solution…

• 3 min read
local variation , statistical characterization , AOCV , characterization , liberate trio , mismatch analysis , Liberate Variety , Monte Carlo , standard cells , global variation , lvf , Liberate , Liberate Characterization Portfolio

定制IC芯片设计

Virtuosity: 针对高级工艺节点器件级布线的工具 – Generate Trunks

Trunk Generation 创新功能，不仅实现干线自动化，提高生产效率，还提供完整的Pin to Trunk 流程的自定义选项.

• less than a min read
Trunk generation , Interactive Routing , Chinese blog , Pin to Trunk , Cadence blogs , ICADVM18.1 , Virtuoso Space-based Router , Layout EXL , Layout Suite , trunk creation , Virtuoso , Generate Trunk , EM Trunk Optimization , Custom IC Design , space based router , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

Photonics Summit: Lumerical-Cadence Flow

James Pond, the CTO of Lumerical, wrapped up the Photonics Summit recently. He started…

• 3 min read
curvycore , Lumerical , silicon photonics , Virtuoso , photonics

定制IC芯片设计

Virtuosity: 针对高阶工艺节点的器件级布线工具 — Finish Trunk

本博客是该系列博客的第一篇，将介绍Finish Trunk 命令，如何实现器件级的布线需求，它并不算是新功能，但可被认为是又一突破性功能.

• 1 min read
Trunk Trimming , Chinese blog , Pin to Trunk , Create Wire , ICADVM18.1 , Virtuoso Space-based Router , layout XL , Layout Suite , Trunk Extending , Layout L , Finish Trunk , EM Trunk Optimization , Custom IC Design

Breakfast Bytes

"If You Can Get Your Ship into Orbit, You're Halfway to Anywhere"

I planned on using the 50th anniversary of Apollo 12 as a hook for this blog, but…

• 7 min read
rocket equation , space travel

System, PCB, & Package Design 

Search Faster and Smarter in Release 17.4-2019

Allegro and OrCAD 17.4-2019 products come with the latest version of CDNSHelp. In…

• 4 min read
17.4 , Search , Cadence Help , 17.4-2019 , OrCAD , Allegro

System, PCB, & Package Design 

IC Packagers: The Third Dimension of 17.4 IC Packaging

If you’ve run the 17.4 release, you have probably seen two 3D rendering tools – 3D…

• 3 min read
17.4 , APD , 3d model

Breakfast Bytes

Cadence to Acquire AWR

Yesterday Cadence announced that it has signed an agreement to acquire AWR from National…

• 3 min read
RF , awr , Virtuoso

Breakfast Bytes

The Photonics Summit 2019: Hybrid Lasers

Recently, Cadence held the fourth Photonics Summit and Workshop over two days. I…

• 5 min read
Lumerical , silicon photonics , photonics
CDNS - Fix Layout Hompage