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Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team 27 Aug 2025 • 1 min read

IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate 21 Aug 2025 • 4 min read

news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera 31 Jul 2025 • 2 min read

featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team 23 Jul 2025 • 2 min read

featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso

cdns - all_blogs_categories

All 6036
Corporate News 191
Life at Cadence 199
Academic Network 166
Analog/Custom Design 760
Artificial Intelligence 23
Cloud 16
Computational Fluid Dynamics 358
Data Center 39
Digital Design 422
Learning and Support 55
RF Engineering 113
SoC and IP 406
System, PCB, & Package Design 982
Verification 1283
Cadence Japan 3

CFD（数値流体力学) 45
中文技术专区 14
カスタムIC／ミックスシグナル 188
PCB、IC封装：设计与仿真分析 136
PCB解析／ICパッケージ解析 44
PCB設計／ICパッケージ設計 61
RF /マイクロ波設計 44
Spotlight Taiwan 61
The India Circuit 88
定制IC芯片设计 79
データセンター 7

Whiteboard Wednesdays 253

Blog - Post List

Latest blogs

Breakfast Bytes

Cadence Tool Suite Qualified for 22FDX Reference Flow

Let's pull a paragraph out of the joint Cadence/GF press release from earlier today…

Paul McLellan 9 Nov 2015 • 4 min read

forward body bias , ARM Techcon , Global Foundries , expert bar , Tempus , 22fdx , 28nm , 20nm , arm cortex , rbb , reverse body bias , gf , Voltus , Innovus , FinFET , arm cortex-a17 , GlobalFoundries , ARM , quantus qrx , fbb , Techcon , FD-SOI

Breakfast Bytes

Where Does 5 Really Mean 30? Process Node Naming

In my first real blog here, about the Cadence/imec 5nm announcement, I asked what…

Paul McLellan 6 Nov 2015 • 3 min read

Intel , process node , Samsung , TSMC , 5nm , GlobalFoundries , 7nm , 10nm , Breakfast Bytes

Breakfast Bytes

How Did Cadence Get to Be Good in Analog?

We recently held the annual Mixed Signal Technology Summit. I blogged about it and…

Paul McLellan 5 Nov 2015 • 4 min read

cadence , diva , composer , analog , Virtuoso , analog mixed signal , OpenAccess

Whiteboard Wednesdays

Whiteboard Wednesdays—Automotive Functional Safety and Reliability Requirements

In this week’s Whiteboard Wednesday, Charles Qi talks about automotive functional…

References4U 4 Nov 2015 • less than a min read

Automotive , Whiteboard Wednesdays , IP , functional safety , software , reliability

Breakfast Bytes

This Year's Phil Kaufman Award Recipient: Wally Rhines

This year's Phil Kaufman award recipient is Wally Rhines. I already knew the big…

Paul McLellan 4 Nov 2015 • 4 min read

DSP , ti320 , Wally Rhines , walden rhines , Mentor Graphics , Kaufman Award , Texas Instruments , Breakfast Bytes , phil kaufman award , Mentor

Breakfast Bytes

The Phil Kaufman Award Dinner Is Later this Month. Who Was Phil Kaufman?

Every year one person in EDA is honored with the Phil Kaufman Award. As it says on…

Paul McLellan 3 Nov 2015 • 4 min read

SCS , cadence , silicon compilers , sci , Quickturn , Phil Kaufman , Breakfast Bytes , phil kaufman award

Breakfast Bytes

Ten Years Ago Self-Driving Cars Couldn't Go Ten Miles

Recently Tesla activated Autopilot for their vehicles, which are equipped with the…

Paul McLellan 2 Nov 2015 • 3 min read

delphi , darpa grand challenge , Stanford , autonomous vehicle , cmu , google , tesla , self-driving car , Breakfast Bytes

Breakfast Bytes

Mixed-Signal Symposium: Mixed Means More Digital

Earlier this week was the Cadence Mixed-Signal Technology Summit. Since I was the…

Paul McLellan 30 Oct 2015 • 5 min read

Berkeley , analog , Mixed-Signal Technology Summit , mixed signal , analog mixed signal , Breakfast Bytes

System, PCB, & Package Design

What's Good About Cadence PCB Design and SI/PI Analysis Products? The 16.6 release…

I’m taking a brief detour from the usual product technical details this week to mention…

Jerry GenPart 29 Oct 2015 • 2 min read

PCB , IC Packaging and SiP Design , Cadence Design Systems , SiP , Allegro 16.6 , Design Entry CIS , DEHDL , FPGA System Planner , High Speed , Allegro Design Workbench , PSPICE , SPB , PCB Editor , High-Density Interconnect , Constraint Manager , Design Entry HDL , Layout , OrCAD , PCB design , AMS simulation , Grzenia , Allegro PCB Editor , ConceptHDL , Allegro