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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Analog/Custom Design

Virtuoso Video Diary - Filtering Your Way Through Corners

Have you ever looked at the Corners Setup form and wished you had some way of finding…

• 4 min read
Analog Design Environment , ADE Explorer , Explorer , Analog Simulation , ADE , Virtuoso , Analog Design Environment , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Assembler

Breakfast Bytes

HOT Party Remembers Gary Smith...and the Denali Party

Every year at DAC, Heart of Technology (HOT) organizes a charity event. This year…

• 2 min read
DAC , HOT , Heart of Technology , Gary Smith , sjsu , Design Automation Conference , Breakfast Bytes

System, PCB, & Package Design 

Epic Western Movies and PCB Design. Seriously.

I love that recently Westerns movies are making a comeback. Something about the romanticism…

• 2 min read
PCB , PCB Layout and routing , Routing , PCB Co-Design , Symphony , Team design , PCB Editor , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

Open-Source Silicon

At the RISC-V workshop in Shanghai, the keynote on the second day was by Bunnie Huang…

• 12 min read
security , open source silicon , root of trust , bunnie huang , open source hardware , open source , Breakfast Bytes

Verification

Have You Fully Verified Your Multi-Core, Cache-Coherent SoC? Find Out How we Can…

You might have thought it would be “just another DAC” this year, again in Austin…

• 3 min read
DAC , SoC verification , Perspec , pss , Accellera PSS

Breakfast Bytes

What's For Breakfast? Video Preview May 29th to June 2nd 2017

https://youtu.be/xTdQCRRme8U Coming from Mexico City, Mexico (camera Yuan Yuan…

• less than a min read
hololens , microsoft , deep learning , embedded vision , Tensilica , Virtuoso

System, PCB, & Package Design 

How Your PCB Design Team Can Become Your Dream Team for Power Integrity

Cadence’s Sigrity team speaks to a lot of power integrity tool users. Experts in…

• 3 min read
PCB , PI , PDN , Power Integrity , Layout , Sigrity , simulation , Schematic

Breakfast Bytes

RISC-V Shanghai 二

This is my second (二 in Chinese) post about the 6th RISC-V workshop held in early…

• 8 min read
computer architecture , risc-v , isa , instruction set architectures , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Convolutional Neural Network Challenges: Bandwidth Requi…

In this week's Whiteboard Wednesdays video, Megha Daga takes a deep dive into bandwidth…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks , bandwidth

Breakfast Bytes

Fifty Years of Computer Architecture: The Last 30 Years

As part of the RISC-V workshop, Dave Patterson gave a talk on computer architecture…

• 6 min read
risc-v , CISC , AMD , titanium , vliw , RISC , Breakfast Bytes

Breakfast Bytes

Fifty Years of Computer Architecture: The First 20 Years

As part of the RISC-V workshop, Dave Patterson gave a talk on computer architecture…

• 6 min read
Intel , risc-v , CISC , RISC , ibm 360 , Breakfast Bytes , dave patterson

Breakfast Bytes

Dream Chip: A Vision for Your Car

Dream Chip is a company based in Germany just outside Hannover. Martin Zeller presented…

• 4 min read
Automotive , dreamchip , 22fdx , ADAS , GlobalFoundries , Breakfast Bytes , FD-SOI

Analog/Custom Design

Virtuosity: Is it Possible to Create a Bus on Several Metal Layers Simultaneously…

Routing Multiple Nets on Different Metal Layers to Gain Productivity Have you…

• 7 min read
transitioning capabilities , space-based router , weAddCustomTransitionMenuItem , customizing multi-layer bus , weRemoveCustomTransitionMenuItem , custom layer pattern , switching bus bits , weGetCustomTransitionMenuItems , multi-layer bus , stacked wires , Layout , Virtuosity , revert to multi-layer bus

Breakfast Bytes

CDNLive EMEA Zwei

This is the second post about CDNLive EMEA in Munich. Here is the first . If the…

• 9 min read
CDNLive , virtual platform , CDNLive EMEA , Bosch , CDNLive Munich , OrCAD , ARM , arrow , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 22nd to 26th 2017

https://youtu.be/Frsw0YkUF5M Coming from Marienplatz, Munich, Germany (camera…

• less than a min read
open source silicon , computer architecture , risc-v , Heart of Technology , Denali Party , isa , Denali , open source , instruction set architecture

Whiteboard Wednesdays

Whiteboard Wednesdays – Tensilica Fusion G6 DSP Takes on Automotive ADAS Radar A…

In this week's Whiteboard Wednesdays video, Pushkar Patwardhan gives an overview…

• less than a min read
DSP , Whiteboard Wednesdays , fusion G6 , Fusion G3 , radar , Tensilica , Fusion DSP Family

Breakfast Bytes

CDNLive EMEA Eins

Every CDNLive has a little bit of a different structure. At CDNLive EMEA in Munich…

• 7 min read
High-Level Synthesis , Automotive , Tom Beckley , CDNLive , CDNLive EMEA , iN7 , JasperGold , HLS , Breakfast Bytes

RF Engineering

7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters…

Hello Spectre Users, Simulating S-parameters in a time domain (transient, periodic…

• less than a min read
S-parameter , Spectre RF , Spectre , International Microwave Symposium

Breakfast Bytes

JasperGold: Stepping up to RTL Signoff

When I was on my last tour of duty at Cadence in the early 2000s, we had a late afternoon…

• 7 min read
Intel , Jasper , JasperGold , Formal verification
CDNS - Fix Layout Hompage