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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Digital Design

Functional Correctness—The Forgotten Benefit of HLS

I like to ask questions, because you learn a lot that way. In fact, I did a survey…

• 2 min read
High-Level Synthesis , Digital Implementation , HLS , verification

Breakfast Bytes

Tensilica Can Improve Your Image

Why is image processing so important? To a first order approximation, all data is…

• 5 min read
Vision P5 , Vision P6 , vision c5 dsp , kirin 970 , image processing , Hisilicon , Huawei

Analog/Custom Design

Art of Analog Design Part 7: Mismatch Tuning

In days of future past, we looked at DC mismatch analysis and compared it to Monte…

• 4 min read
mismatch tuning , Monte Carlo analysis , DC Mismatch

Breakfast Bytes

The Book That Changed Everything

Academics have had a big influence on semiconductor design and design automation…

• 7 min read
introduction to vlsi systems , carver mead , lynn conway

Breakfast Bytes

CHIP: College Hire and Internship Program

For some time, Cadence had an informal internship program: if managers wanted to…

• 4 min read
Interns , Cadence Academic Network , recruitment , graduates , hiring

Breakfast Bytes

What's For Breakfast? Video Preview November 6th to 10th 2017

https://youtu.be/P3O79m4r-PM < Coming from the Cadence building 10 lobby (camera…

• less than a min read
security , ARM Techcon , Simon Segars , security manifesto , mobile , Russia , social engineering , ARM

Breakfast Bytes

Cadence Academic Network Is Ten Years Old

Yes, it's true, the Cadence Academic Network is having its tenth anniversary. The…

• 5 min read
mannheim , Cadence Academic Network , asic competence center

Whiteboard Wednesdays

Whiteboard Wednesdays - Understanding ISO 26262 Implications for Automotive Design…

In this week's Whiteboard Wednesday, Anne Hughes explains the considerations for…

• less than a min read
Whiteboard Wednesdays , functional safety , ASIL , ISO 26262 , automotive design

Breakfast Bytes

Rob Rutenbar Is Recipient of 2017 Kaufman Award

This year's recipient of the Kaufman Award is Rob Rutenbar. He has a big connection…

• 8 min read
neolinear , Coursera , rob rutenbar , university of illinois , MOOC , Kaufman Award , cmu , kaufman award dinner , c2s2 , Voci Technologies , university of pittsburgh , analog design , Breakfast Bytes

Breakfast Bytes

October 2017 Breakfast Buffet

https://youtu.be/2HhOBOftlv4 Coming from the roof of Cadence building 10 (camera…

• less than a min read
China , AMD , linley group , semi , cdnlive taiwan , armmobile , pss , microprocessor , portable stimulus

Analog/Custom Design

Simplifying the Memory Design Process

On today’s SOC designs, the memory control logics and memory arrays take up a lot…

• 2 min read
Memory , custom/analog , Spectre , Custom IC Design , Custom IC

Verification

Cadence and Arm Announce Early Access to Xcelium Parallel Logic Simulators on Arm…

On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic…

• 1 min read
Multi-Core , xcelium , ARM , simulation , announcement

Breakfast Bytes

Andrew Kahng on the Last Semiconductor Scaling Levers

It's going to be academic week here on Breakfast Bytes. There is an anniversary coming…

• 9 min read
scaling , EDA , cloud , andrew kahng , machine learning , moore's law , Breakfast Bytes

Breakfast Bytes

Decoding Formal Club: Arm and Arteris

At the latest meeting of the Decoding Formal Club, organized by Oski and sponsored…

• 8 min read
Jasper User Group , JUG , oski decoding formal club , formal , Oski , Breakfast Bytes , Formal verification

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (2 of 8)

Let’s assume that we are working on a PCI Express Gen 4 serial link, running at 16Gbps…

• 3 min read
Serial link analysis , Signal Integrity , Sigrity

Breakfast Bytes

What's For Breakfast? Video Preview October 30th to November 3rd 2017

https://youtu.be/JQVYmENG0gw Coming from the Cadence booth at Arm TechCon …

• less than a min read
ARM Techcon , Rutenbar , Cadence Academic Network , scaling , introduction to vlsi systems , intern , mead and conway , kahng , Kaufman Award , esd alliance

Analog/Custom Design

Virtuosity: Read Mode Done Right

Because of the ease with which you can set up complex sweep, corner and Monte Carlo…

• 4 min read
ADE Explorer , Custom IC Design. Read only , ADE , Analog Design Environment , ADE Assembler

Breakfast Bytes

Why Was Arm Successful in Mobile?

I think that Arm was successful in mobile (and subsequently in other markets) due…

• 5 min read
mobile , Silicon Valley , ARM , Breakfast Bytes

System, PCB, & Package Design 

Signal Integrity Methodology for Multi-Gigabit Serial Link Interfaces (1 of 8)

As data rates for serial link interfaces such as PCI Express® (PCIe®) Gen 4 move…

• 6 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity
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