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Cadence Japan

日本ケイデンス、「働きがいのある会社」 ベスト１００に5年連続で選出

日本ケイデンス・デザイン・システムズ社（横浜市港北区新横浜）は、Great Place To Work® Institute Japan（以下、GPTW Japan…

Cadence Japan
• less than a min read
news story , Culture , featured , japanese blog

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P
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Blog - Post List
Latest blogs

Verification

Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)

When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But…

• 4 min read
performance , Specman , Functional Verification , Incisive , e , e language

System, PCB, & Package Design 

Designing a Complex Leadframe Package? See How SiP Layout Tool Can Cover All the…

Leadframe package designs are here to stay, and they are getting more complex with…

• 7 min read
IC Packaging and SiP Design , Cadence Design Systems , leadframe , SiP , Digital SiP design , design variants , IC package design , package design , SiP Layout , wirebonding

Verification

The Dark Side of Constraints on 'do-not-generate' Fields

The art of expressing hardware functionality through constraint language is often…

• 7 min read
IntelliGen , Specman , Functional Verification , e language , constraint coding

Verification

Debugging Multi-Language Verification Environments

As shown in previous blog posts in the Multi-Language Verification Environment series…

• 4 min read
uvm , UVM-ML , multi-language verification , debugging

Digital Design

Five-Minute Tutorial: Innovus Placement Optimization

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now…

• less than a min read
GigaPlace , Timing Optimization , Innovus , Placement

Whiteboard Wednesdays

Whiteboard Wednesdays—What Is PCI Express Address Translation Services?

In this week's Whiteboard Wednesdays video, Gopi Krishna defines and describes how…

• less than a min read
Whiteboard Wednesdays , address translation services , PCIe , PCI Express

SoC and IP

Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth…

The PCI-SIG Developers Conference happening today and tomorrow will be yet another…

• 2 min read
PCIe Gen4 , pcie gen2 , 16nm , PCIe Gen3 , PCI-SIG

Analog/Custom Design

Things You Didn't Know About Virtuoso: Help Us to Help You

There is a team at Cadence working on developing the next generation of Cadence documentation…

• less than a min read
Virtuoso , Cadence Help , online documentation , Cadence support

System, PCB, & Package Design 

Manage All Design Variant Options for Your Package Substrate Seamlessly Using 16…

Stacked memory is becoming increasingly common in IC package substrates; with that…

• 2 min read
IC Packaging and SiP Design , stacked dies , SiP , IC Package , IC Packaging , SiP Design , design variants , package design , SiP Layout

SoC and IP

Sensor Processing, How Hard Can It Be?

When I think back back just a few years ago, there were only a handful of devices…

• 2 min read
DSP , IP , IP blocks , controller , IoT , SoC , Fusion , ip cores , Processor IP , Tensilica , semiconductor IP , Internet of Things , Design IP and Verification IP , always-on

Whiteboard Wednesdays

Benefits of Designing Your SoC with a Multi-Protocol PHY

In this week's Whiteboard Wednesday video, William Chen explains the many benefits…

• less than a min read
Whiteboard Wednesdays , IP , PHY , SoC , multi-protocol

SoC and IP

Tensilica Team Wins DAC 2015 Best Paper Award

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at…

• 1 min read
IP , Chris Rowen , ip cores , vision , imaging , image processing

Analog/Custom Design

Virtuosity: 14 Things I Learned in May 2015 by Browsing Cadence Online Support

Cadence Documentation 1. Cadence Documentation Survey Cadence is committed…

• 4 min read
ADE XL , Virtuoso , Spectre

Verification

Designing a Google Ara Module and Worrying About MIPI UniPro?

So you've looked at Google project ARA and you have the most brilliant idea for a…

• 1 min read
Verification IP , UniPro , Ara , VIP , MIPI , google , TripleCheck

Verification

Aargh!!! How Can I Read Arguments from the Command Line Without argv?

Many times a user would like to be able to modify the behavior of a program based…

• 3 min read
Specman , Functional Verification , e language , simulation

Verification

Multi-Language Verification Environment (#4)—Multi-Language Hierarchy

In the previous posts in this series on Multi-Language Verification Environment,…

• 2 min read
uvm , Functional Verification , e , universal verification methodology , e language , multi-language , verification

Digital Design

Five-Minute Tutorial: The Innovus Standard Flow

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface…

• less than a min read
design flow , Digital Implementation , Innovus , five minute tutorial

Verification

Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi…

In the previous blog post , we demonstrated connecting a checker implemented in SystemVerilog…

• 3 min read
SystemVerilog , uvm , multi-language verification , UVM Scoreboard , verification

Verification

DAC 2015 – Join Us to Experience the Continuum of Verification and System Development…

The biggest yearly event in electronic design automation (EDA) is due to take over…

• 8 min read
cadence , EDA , Moscone Center , DAC 2015 , verification , system development
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