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The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda
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Blog - Post List
Latest blogs

SoC and IP

Brian Fuller @EETimes: Renesas to put MRAM in 90nm microcontrollers by 2013

EETimes’ Brian Fuller is blogging live from the Renesas DevCon down in southern California…

• 1 min read

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Customizable Datatips? Look to SPB16.3 and See

In pre-select mode Allegro displays a datatip that provides information about the…

• 5 min read
PCB , PCB Layout and routing , SPB16.3 , Allegro 16.3 , SPB 16.3 , property , PCB Editor , PCB design , Allegro PCB Editor , PCB Capture , Allegro

Digital Design

3D-IC TSV Realization: The Race Has Begun!

3D IC discussions are creating quite a buzz these days. No conference is complete…

• 3 min read
packaging , 3D-IC , 3DIC , TSV , Floorplanning , Test , Digital Implementation , 3D , thermal

Verification

Connections Partner NextOp on Assertion Synthesis and Assertion-Based Verification…

As anyone working in Formal and Assertion-Based Verification (ABV) knows, the task…

• 1 min read
Cadence Connections , NextOp , ABV , CDNLive , Functional Verification , formal , EDA360 , assertion synthesis , IEV , IFV

SoC and IP

Sandforce Enterprise-Class SSD 2500/2600 processors deliver double performance

SandForce has just announced a new enterprise-class SF-2000 SSD processor family…

• less than a min read

Verification

Video: Interview With NextOp CEO Yunshan Zhu on Assertion-Based Verification (ABV…

What makes a startup "hot"? To be sure, trade press and blogger attention helps.…

• 1 min read
Cadence Connections , NextOp , DAC , ABV , CDNLive , Functional Verification , Formal Analysis , formal , EDA360

SoC and IP

Anandtech reports that Intel’s new SSDs that incorporate 25nm Flash will have 4x…

This blog previously reported that Intel will be rolling out new versions of its…

• less than a min read

Verification

"We Want UVM 1.0! When Do We Want it? Now!"

Short of holding signs and yelling slogans, the 12 customers I visited in the past…

• 3 min read
SystemVerilog , uvm , OVM ML , OVM , VIP , OVM e , EDA360 , Incisive , OVM SV , AMIQ , Accellera VIP TSC , IES , VMM , IES-XL

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL--Take This Job and...Run It!

Sometimes these articles just write themselves... Last week, 3 different people asked…

• 3 min read
Analog Simulation , analog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About AMS Simulator Fonts, Models, and More? It's in SPB16.3!

The SPB16.3 release of the Allegro AMS Simulator environment contains a few additional…

• 2 min read
SPB16.3 , AMS , AMS simulator , SPB 16.3 , PSPICE , SPB , AMS simulation , Design Entry , library

RF Engineering

Measure Twice, Cut Once for Transistor ft

Recently there was an inquiry about the methodology for performing the f t (transition…

• 3 min read
RF , Ft , ADE-L , Analog Simulation , Measuring Transistor ft , transistor , Analysis , ADE , Virtuoso , parametric , sweep

Verification

Why EDA Verification is Like Pro Sports

First, I would like to introduce myself. My name is Jim Kjellsen. I've recently joined…

• 2 min read
Functional Verification , football , pro sports , sports , Kjellsen , verification

SoC and IP

Renesas introduces new 1.1Gbit low-latency DDR DRAM (LLDRAM) for networking apps

Renesas has introduced a new 1.1Gbit, low-latency DDR DRAM (LLDRAM) primarily for…

• 1 min read

Verification

Tech Tip: Distributing Incisive Enterprise Verifier (IEV) Engines and Assertions…

A common problem when distributing engines and assertions in Incisive Enterprise…

• 1 min read
ABV , Functional Verification , Formal Analysis , formal , LSF , Enterprise Manager , IEV

SoC and IP

OCZ invents proprietary 20Gbps link for SSDs, snubbing SAS, SATA, and PCIe

Yesterday, OCZ released a curious statement saying that it was unveiling a proprietary…

• less than a min read

SoC and IP

Elpida announces 30nm, low-voltage, low-power, 2Gbit DDR3 SDRAM with TSV (through…

The headline pretty much says it all. Memory vendor Elpida hit all the DRAM high…

• 1 min read

Verification

A Quick Check on the Status of UVM 1.0

Regular readers know that I've blogged a lot about the Open Verification Methodology…

• 2 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

SoC and IP

LSI Corp to host IC innovation conference and technology showcase in Milpitas next…

On October 5 through 7, LSI Corp will be hosting a conference and technology showcase…

• 1 min read

Verification

Will Your Next System Project Succeed?

Will you have the System Realization tools you need? Will you know how to apply them…

• 3 min read
TLM , webinars , system realization , TSMC , services , ARM , ESL , System Design and Verification
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