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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

UVM Is Now IEEE 1800.2 and There's a Ten-Year Story to That

UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered…

• 6 min read
SystemVerilog , Superlog , ieee 1800.2 , uvm , Accellera , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 8th to 12th 2017

https://youtu.be/sIFo4JKjVxw Coming from NASA Ames Research Center, Sunnyvale…

• less than a min read
space shuttle , risc-v , NXP , ser , 22fdx , soft error rate , 12fdx , Samsung , single event upset , Tensilica , single event effect , ST Microelectronics , GlobalFoundries , ARM , microprocessor , NASA , reliability , FD-SOI

Breakfast Bytes

Bayern München Will Not Be at CDNLive Munich: Here's What They Will Miss

Yes, it's true. After attending CDNLive EMEA for the last couple of years, Bayern…

• 3 min read
Automotive , NXP , Munich , CDNLive , CDNLive EMEA , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays – Introduction to Cadence Tensilica Vision C5 DSP

In this week's Whiteboard Wednesdays video, Pulin Desai describes the main features…

• less than a min read
Whiteboard Wednesdays , Vision DSP , convolutional neural networks , CNN

Breakfast Bytes

Test Flying Pegasus

Scott Barric of MicroSemi is one of the people who have been using the pre-release…

• 5 min read
Physical verification , pegasus , DRC , cloud , microsemi , design rule check , PVS , Breakfast Bytes , cloud computing

Digital Design

Designing for Low Power… Begin at the Beginning

So you have your RTL written, and it’s time to optimize to reduce power. If that…

• 3 min read
Low Power , high level synthesis , power , HLS

Analog/Custom Design

Virtuosity: The Reboot

It’s been quite a while since I wrote about “Things I Learned by Browsing Cadence…

• 2 min read
Analog Design Environment , ADE GXL , ADE Explorer , Rapid Adoption Kit , Analog Simulation , ADE XL , ADE , ADE-GXL , Analog Design Environment , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Breakfast Bytes

Vision C5 DSP for Standalone Neural Network Processing

I pointed out recently that although La La Land is a romance, the movie opens with…

• 6 min read
DSP , Vision C5 , embedded vision , Embedded Vision Alliance , Tensilica , semiconductor IP , embedded vision conference , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 1

In this week's Whiteboard Wednesdays video, Tom Hackett traces the evolution of the…

• less than a min read
Whiteboard Wednesdays , ccix

Breakfast Bytes

Growth Comes from Solving New Problems—ESD Alliance CEO Panel

First, some sad news. Bob Gardner, for many years the executive director of the ESD…

• 12 min read
cadence , EDAC , arm holdings , ARM , synopsys , Breakfast Bytes , esd alliance , Mentor

Breakfast Bytes

Microsoft CDNLive Keynote: Cloudy with a Chance of Chips

Traditionally at CDNLive Silicon Valley, the first keynote is given by Lip-Bu Tan…

• 7 min read
microsoft , deep learning , cloud , azure , CDNLive Silicon Valley , Breakfast Bytes

Breakfast Bytes

The IRDS Panel at IRPS

Confused by those names? The conference is the International Reliability and Physics…

• 4 min read
irds , ITRS , international roadmap for devices and systems , irps , IEEE , Breakfast Bytes , rebooting computing

Whiteboard Wednesdays

Whiteboard Wednesdays - Convolutional Neural Network Challenges

In this week's Whiteboard Wednesdays video, Megha Daga takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

"The Safest Train Is One that Never Leaves the Station"

The Sunday and Monday at IRPS are tutorial days, with multiple tracks. On Monday…

• 7 min read
Automotive , functional safety , volkswagen , NVIDIA , sotif , ISO 26262 , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 1st to 5th 2017

https://youtu.be/n1uLybW0__s Coming from Millennium Park, Chicago (camera Jessamine…

• less than a min read
Physical verification , ieee 1800.2 , uvm , Genus , Embedded Vision Summit , pegasus , DRC , CDNLive EMEA , TSMC , via pillar , CDNLive Munich , Tensilica , design rule check , n7 , Innovus , cdnlive München , 7nm , vision processor

Breakfast Bytes

The $10 Raspberry Pi Zero W

Roger Thornton of the Raspberry Pi foundation talked about designing their latest…

• 6 min read
Raspberry Pi , raspberry pi zero w , bluetooth , PCB design , WiFi , Breakfast Bytes , Allegro

Verification

SoC Verification with Portable Stimulus Using Perspec System Verifier

This year’s CDNLive San Jose was another gem. Many great keynotes, customer presentations…

• 2 min read
SoC verification , Perspec , perspec system verifier , Qualcomm , portable stimulus

Breakfast Bytes

Software Isn't the S in SDE

System Design Enablement (SDE) is about designing optimal systems, focusing effort…

• 8 min read
SDE , open source , software , gcc , system design enablement , linux , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: Run Point Selection -WYSIWYG

With Virtuoso ADE Explorer and Virtuoso ADE Assembler , it is easy to create setups…

• 4 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , Mixed-Signal , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design
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