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Cadence Japan

【ホンダHGR＋ケイデンス前編】Physical AIの“Physical”とは何か─現実に勝てないAIは、動けない

※本記事は、Honda総合研究センター/HGRに掲載された記事を、同社の許諾を得て転載しています。 皆さん、こんにちは。HGRセンター長の小川厚（おがわ あつし…

Cadence Japan
• less than a min read
featured , japanese blog

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Breakfast Bytes

Circuits and Systems for Security and Privacy

One of the perks of writing this blog is that I get offered review copies of interesting…

• 6 min read
security , side channel attacks , encryption , puf , crc press , random number , physically unclonable functions

Breakfast Bytes

Tom Quan on TSMC's Automotive Strategy

Tom Quan recently came to Cadence to talk about TSMC's automotive strategy. Tom and…

• 4 min read
Automotive , tom quan , TSMC , 7ff , 16FFC , ISO 26262 , ADAS , 7nm , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview February 13th to 17th 2017

https://youtu.be/HL0GFG9tNP4 Coming from Cadence security camera Monday…

• less than a min read
deep learning , machine learning , convolutional neural networks , moore's law , embedded neural networks , neural networks , machine vision

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplify UVM Scoreboarding with Cadence VIP

In this week's Whiteboard Wednesdays video, principal AE Matt Diehl explains how…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , DisplayPort , Matt Diehl

Breakfast Bytes

He Who Goes First Loses, EDA Edition

Yesterday I wrote a post He Who Goes First...Loses about how being first isn't always…

• 4 min read
point tools , hunters , EDA , ambit , farmers

Breakfast Bytes

He Who Goes First...Loses

There is a saying, of course, that he who goes first wins. And sometimes, and in…

• 5 min read
apple pay , credit cards , m-pesa , tube , london tube

Breakfast Bytes

Handling Variability in the Modern Design Cycle

Igor Keller gave an internal presentation on Handling Variability in the Modern Design…

• 6 min read
on chip variation , AOCV , STA , OCV , variability , voltage droop , static timing , layout dependent effects , miller capacitance , SOCV , crosstalk , slew , SSTA

Verification

Preview of an Exciting DVCon

In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest…

• 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

Breakfast Bytes

What's For Breakfast? Video Preview February 6th to 10th 2017

https://youtu.be/XOS4sfILahc Coming from Design Con 2017 Monday: He Who…

• less than a min read
security , Automotive , Routing , TSMC , business strategy , Innovus , privacy

Verification

IEEE Std 1647™ 2016 - e Language - New Standard Publication

Congratulations to the IEEE-1647 e Functional Verification Language Working Group…

• 2 min read
IEEE 1647 , Specman , e , e language , specman elite

Breakfast Bytes

The ASML Standard Node

One of the first posts I wrote here at Breakfast Bytes was Where Does 5 Really Mean…

• 3 min read
mmhp , cphp , standard node , EUV

Breakfast Bytes

The Book for Practicing Formal Verification Engineers

At the no-longer-so-recent Jasper User Group JUG last year, the keynote was by Erik…

• 3 min read
formal verification book , Formal verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Ethernet: Not Your Grandfather's Ethernet

In this week's Whiteboard Wednesdays, Scott Jacobson wraps up his three-part series…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , Automotive Ethernet , Ethernet

Breakfast Bytes

ENIAC, EDSAC and Colossus... and the Difference Engine

There are lots of claims to be the first computer, depending on your definition of…

• 5 min read
edsac , analytical engine , mercury delay line , difference engine , first stored program computer , eniac

Analog/Custom Design

Virtuoso Video Diary: Is It That Easy to Edit in the Virtuoso Schematic Editor?

Creating a neat and organized schematic is extremely important, and often requires…

• 3 min read
Virtuoso Schematic Editor , VSE L , Advanced Node , VSE XL , Virtuoso Video Diary , Custom IC Design

Breakfast Bytes

Andrzej Strojwas Receives the 2016 Kaufman Award

Last night was the annual Kaufman Award dinner to present the award to this year…

• 6 min read
Kaufman Award , kaufman award dinner , andrzej strojwas , pdf solutions

Breakfast Bytes

What's For Breakfast? Video Preview January 30th to February 3rd 2017

https://youtu.be/NxgrCMJYRew Coming from Kaufman Award Dinner Monday: The…

• less than a min read
asml standard node , formal , Kaufman Award , STA , andrzej strojwas , variability , standard node , Formal verification

Breakfast Bytes

SPIE Advanced Lithography Conference

SPIE is the international society for optics and photonics, with the purpose of …

• 4 min read
lithography , imec.spie advanced lithography , SPIE

Breakfast Bytes

Frank Chen of a16z on 16 Things About Autonomous Vehicles

In a recent a16z presentation, Frank Chen, a partner at Andreessen-Horowitz, says…

• 6 min read
autonomous cars , self-driving cars , a16z , autonomous vehicles
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