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Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

SoC and IP

Word from the Source—USB-IF on USB Type-C Quality and Interoperability (Jeff Ravencraft…

In the first two parts of the interview with Jeff Ravencraft, the President and COO…

• less than a min read
USB 3.0 , cadence , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

SoC and IP

Word from the Source—USB-IF on USB Type-C and Alternate Modes (Jeff Ravencraft Interview…

If it wasn’t for the fact that USB has always been spelled with capital letters,…

• less than a min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Academic Network

Virtuoso Front-to-Back Workshop Series in Saudi Arabia

Starting Dec. 5 th , 11 PSATRI members attended a five-day workshop on the Cadence…

• 1 min read
Cadence Academic Network , Virtuoso , King Saud University , simulation

SoC and IP

Word from the Source—USB-IF on What USB-IF Is and What’s New in USB (Jeff Ravencraft…

In case you don’t know, USB Implementers Forum (USB-IF, for short) is the organization…

• less than a min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Breakfast Bytes

Nibbles—Breakfast Bytes Predictions for 2016

Neils Bohr, the physicist (or should that be the quantum mechanic) famously said…

• 3 min read
Automotive , predictions , USB Type-C , CES , SDE , design nodes , Test , 2016 , 3D packaging , system design enablement , Breakfast Bytes , Formal verification

Breakfast Bytes

Congratulations Chris Rowen, for He's a Jolly Good (IEEE) Fellow

So the lede is that Chris Rowen has been elected an IEEE Fellow. In a sense it is…

• 4 min read
Chris Rowen , IEEE Fellow , RISC processors , Tensilica , configurable processors

Whiteboard Wednesdays

Whiteboard Wednesdays - Understanding the Computational Activity Behind Neural N…

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the inter-workings…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , neural network , pattern recognition

System, PCB, & Package Design 

What's Good About ADW’s Component Browser for Project Manager? The Secret's in the…

The 16.6-2015 Allegro Design Workbench (ADW) release contains a significant enhancement…

• 1 min read
Allegro 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , component browser , design data management , PCB design , Grzenia , Librarians , library , ADW , Allegro

Breakfast Bytes

EDAC "Crossing the Chasm" with John Lee

EDAC's Emerging Companies Committee has been organizing evening seminars a couple…

• 6 min read
John Lee , EDAC , EDA standards , Jim Hogan , Ansys

Breakfast Bytes

IEDM: the International Electron Devices Meeting

IEDM is a meeting held annually since 1955. Historically, it has alternated between…

• 4 min read
International Electron Devices Meeting , IEDM , semiconductors , Breakfast Bytes

Breakfast Bytes

EUV Might Really Happen

I have been a skeptic about whether EUV was going to work. Just in case you have…

• 4 min read
lithography , 5nm test chip , defect , pellicle , 7nm , EUV , Breakfast Bytes

Academic Network

First Cadence Academic Network Workshop in Israel

On October 27, the Cadence Academic Network organized the 1st Cadence Academic Workshop…

• 1 min read
university , Cadence Academic Network , academic workshop , Bar Ilan University

Whiteboard Wednesdays

Whiteboard Wednesdays - Implementation of Multi-Link, Multi-Protocol PHY

In this week's Whiteboard Wednesdays video, William Chen deep dives into the implementation…

• less than a min read
Whiteboard Wednesdays , multiprotocol PHY , PHY IP

Breakfast Bytes

Use the Integrated Flow with US

A couple of years ago, it was clear that the Cadence implementation flow required…

• 4 min read
Genus , full-flow , Joules , Voltus , Innovus , Quantus QRC , Quantus , integrated flow , Breakfast Bytes

Academic Network

Cadence Academic Network Presents at Khalifa Semiconductor Research Center

On Nov. 18 Dr. Patrick Haspel presented at Khalifa Semiconductor Research Center…

• 1 min read
Cadence Academic Network , UAE , Khalifa

Academic Network

Using Constraints Generation When Designing Power-Constrained SoCs

If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling…

• 3 min read
constraints generation , Professor Farid Najm , power constrained SoCs , power grid , Power Integrity , voltage drop , power scheduling

Breakfast Bytes

Rob Aitken of ARM Research on System Design

I wrote yesterday of how there is a transition going on as system companies discover…

• 2 min read
SDE , system design , Rob Aitken , system design enablement , ARM , Breakfast Bytes

Academic Network

Why Agile Software Methodologies Can Improve the Chip Design Process

UC Berkeley Professor Borivoje Nikolic sees agile software methodologies as an answer…

• 3 min read
Berkeley engineering , AMS , agile software development , open source , mixed signal , UC Berkeley

Academic Network

Cadence Tech Days at ITMO and MIET

Cadence Academic Network organizes TechDays in Russia to promote leading-edge technologies…

• 1 min read
MIET , Cadence Academic Network , Russia , ITMO
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