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Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI
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Blog - Post List
Latest blogs

Verification

Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

More and more often it takes a village to achieve verification success. As reported…

• 1 min read
Functional Verification , Incisive , xilinx , IES , FPGA , Matlab , IES-XL

SoC and IP

NAND Flash as the media killer: Sony to kill the floppy in Japan, finally

Sometimes it takes decades but NAND Flash semiconductor memory is turning out to…

• 1 min read

System, PCB, & Package Design 

Favorite Features of an IC Package Designer: Flexible 3D Viewing

This is the first in a series of discussions we would like to open up regarding…

• 1 min read
SiP , Digital SiP design , 3D-IC , Allegro 16.3 , TSV , APD , IC Packaging & SiP design , IC Package Physical layout and co-design , Kulicke & Soffa

Verification

Verified by e/Specman: The Palladium XP Verification Computing Platform

After much anticipation, it feels great to be free to proclaim that e /Specman (as…

• less than a min read
metric driven verification (MDV) , Functional Verification , e , Palladium XP , MDV , IES-XL

SoC and IP

Corsair Video vividly shows SSD speedup on laptop

Wondering whether an SSD really makes that much difference to laptop performance…

• less than a min read

Digital Design

Hands Up, Anyone Believe That Toyota's Problems Are All Physical?

In the past number of weeks/months we have all seen how Toyota has struggled to manage…

• 2 min read
toyota , Digital Implementation , BMW , microprocessor , verification

Verification

Ubuntu on ARM is Growing

Based on the title, you probably guessed I'm talking about growing in popularity…

• 6 min read
virtual platform , System Design & Verification , Embedded Linux , QEMU

System, PCB, & Package Design 

Who’s up for Chinese?

Recently, someone asked me " .. . why bother translating OrCAD products to Chinese…

• 1 min read
Capture CIS' , PSPICE , OrCAD , PCB design , PCB Capture , Schematic

SoC and IP

What is a Flash cache?

A Flash cache acts like SRAM memory caches that are designed to speed up DRAM access…

• 3 min read

SoC and IP

Free DAC Tix -- Better hurry ‘cause they’re going fast

Love DAC? Design chips? Looking for a job? Today’s your lucky day. Denali, Atrenta…

• 1 min read

SoC and IP

Numonyx 128-Mbit serial- and parallel-I/O PCM non-volatile memories now available…

Numonyx has announced or reannounced two 128-Mbit non-volatilve memory devices based…

• 2 min read

System, PCB, & Package Design 

What's Good About Simplifying the Use of Third-Party SI Models? It's in SPB16.3!

Today, many users receive SI models that are not in DML format. They are given IBIS…

• 8 min read
PCB SI , SI , HSPICE , Signal Intregrity , IBIS , SigXP UI , PCB Signal and power integrity , SPB 16.3 , IBIS-AMI , PCB design

Verification

UVM Based on OVM 2.1.1: What a Great Idea!

Regular readers know that I have been urging the Accellera VIP TSC to base its Universal…

• 2 min read
uvm , Verification methodology , OVM , Functional Verification' signal integrity , Contributions , Accellera

Verification

When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog…

Building on the packet generation example of part 1 , and the coverage examples of…

• 3 min read
IEEE 1647 , SystemVerilog , Specman , Object Oriented Programming , Functional Verification , e , OOP , Aspect Oriented Programming , AOP , IES-XL

SoC and IP

Intel’s Atom-based Tunnel Creek SOC with integrated PCIe interface opens new era…

One of the most ignored Intel announcements of recent memory must be Doug Davis’…

• 2 min read

SoC and IP

Network World SSD Smackdown shows Fusionio’s PCIe-based SSD provides highest thr…

Network World has just posted an SSD comparison test written by Logan G. Harbaugh…

• 3 min read

SoC and IP

Firmware as the performance differentiator for SSD controllers

Anandtech has just posted a meaty article about SandForce SSD controllers as used…

• 3 min read

Digital Design

EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

Every April the leading edge of the leading edge of semiconductor industry meet…

• 3 min read
DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , stacked die , flip chip , PoP

SoC and IP

Comprehensive SSD eval puts four drives to the test

Geoff Gasior at The Tech Report has just published a long and very comprehensive…

• 2 min read
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