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Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays—Innovations in the DRAM World

In this week's Whiteboard Wednesdays video, Lou Ternullo reviews the latest DRAM…

• less than a min read
Whiteboard Wednesdays , IP , DRAM , system level , density

Verification

Indago Protocol Debug and IP Verification

Nothing beats knowing, a late electronics-industry veteran used to say. That’s no…

• 3 min read
IP , cadence , debug , Functional Verification , electronics system design , Indago , engineering , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Why Buy Memory Models?

In this week's Whiteboard Wednesdays video, Susan Peterson breaks down why you should…

• less than a min read
Whiteboard Wednesdays , IP , memory models

System, PCB, & Package Design 

What's Good About the Allegro Design Entry HDL Front to Back Flow Cadence Training…

Hear what Bruce Imai—a Cadence Educational Services course developer—Cadence Application…

• less than a min read
PCB Layout and routing , Routing , electrical constraints , 16.6 , High Speed , hierarchical schematics , PCB Editor , Design Entry HDL , Layout , PCB design , Grzenia , Schematic , Allegro

SoC and IP

Speed, Function, and Technology as Key Factors for USB Applications

USB is regarded as the world’s most popular serial interface, with over 1 billion…

• 2 min read
Design IP , host , controller , PHY , OTG , 1.1 , USB , Dual Mode , ip cores , 2.0 , Dual Role , device , 3.0

Whiteboard Wednesdays

Whiteboard Wednesdays - Analog Front-End Interfaces Explained

In this week's Whiteboard Wednesdays video, Bob Salem takes a closer look at analog…

• less than a min read
Whiteboard Wednesdays , IP , wireless communications , analog front end , AFE

Digital Design

Five Things You Didn’t Know About High-level Synthesis

Most of you have heard about the promises of high-level synthesis (HLS). Things like…

• 4 min read
High-Level Synthesis , ECO , Conformal ECO Designer , cadence , Blu Wireless , Forte , Stratus , HLS

Whiteboard Wednesdays

Whiteboard Wednesdays – Why a New DSP Is Needed to Support Today's Sensors

In this week’s Whiteboard Wednesdays, Chris Rowen highlights the requirements of…

• less than a min read
DSP , Whiteboard Wednesdays , IP , Chris Rowen , IoT , sensors , Tensilica , Internet of Things

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Suppression of Unassigned Indirect Vias? 16…

The suppression of unassigned indirect vias is now supported in Allegro PCB Editor…

• 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , PCB Editor , Layout , via , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—DDR Subsystems and Latency

In this week's Whiteboard Wednesdays video, Lou Ternullo discusses DDR subsystems…

• less than a min read
Whiteboard Wednesdays , IP , DDR , latency

SoC and IP

Don’t Miss Embedded Vision Summit on May 12

One of the best, most insightful (no pun intended) conferences each year is the Embedded…

• 1 min read
DSP , Chris Rowen , IVP , vision processing , embedded vision , Tensilica , vision

SoC and IP

Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for…

Consumer demand for entertainment and communication is changing the architecture…

• 5 min read
DDR4 , LPDDR4 , IoT , cloud , Design IP and Verification IP , 16FF+

SoC and IP

CDNLive IP Track Presentations Available Online

With more than 100 presentations, live product demos, designer expo, and numerous…

• 2 min read
CDNLive , Tensilica , Design IP and Verification IP

SoC and IP

Interconnect Validator and its Significance

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP…

• 2 min read
Interconnect Workbench , AMBA ACE , Interconnect Validator , VIP , AMBA CHI , SoC , OCP , Design IP and Verification IP

Whiteboard Wednesdays

Whiteboard Wednesdays—What Makes a Protocol Standard Stick

In this week's Whiteboard Wednesdays video, Susan Peterson takes a closer look at…

• less than a min read
Whiteboard Wednesdays , IP , UniPro , protocol , VIP , MIPI , DisplayPort , LLI , HMC , M-PCIe , HBM , PCIe , HDMI , PCI Express , SSIC

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Associative Dimensioning Updates? 16.6 Has Several…

With the 16.6 Allegro PCB Editor release, custom text can now be specified for any…

• 2 min read
PCB Layout and routing , Allegro 16.6 , PCB Editor , Layout , PCB design

SoC and IP

Sign Up for Linley Mobile Conference – See Chris Rowen

If you’ve never heard of the Linley Mobile Conference , you’ve been missing out on…

• 1 min read
wireless , sensor fusion , always on , always alert , sensors , Fusion , Tensilica , sensing , Linley Mobile Conference , context triggers

Analog/Custom Design

Virtuosity: 19 Things I Learned in March 2015 by Browsing Cadence Online Support

1. Cadence Online Support has a sleek new design along with support for iPAD and…

• 3 min read
CDNLive , guard ring , ADE XL , ADE , OASIS , ViVA , DRD , FinFET , Custom IC Design , Schematic

System, PCB, & Package Design 

Power Integrity Solution Spans Multiple PCBs and Packages

When designing next-generation products, the common theme is "faster, smaller, cheaper…

• 2 min read
PCB , electronics design , Power Integrity , IR Drop analysis , Power Delivery Network , electrical thermal co-simulation , Thermal Analysis , PCB design , Sigrity , Allegro PCB Editor , PowerDC , Allegro
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