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Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Embedded Net Name Display? Check Out 16.6!

A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within…

• 1 min read
PCB , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , Routing , 16.6 , SPB , PCB Editor , PCB routing , Layout , design , vias , "PCB design" , PCB design , Grzenia , pin planning , physical layout design , Allegro PCB Editor , color visibility , stipple , Allegro , etch shapes

System, PCB, & Package Design 

Why Does Signal Integrity Analysis Need to be Power Aware?

Ever since the I/O Buffer Information Specification (IBIS) committee broke away from…

• 2 min read
IBIS Model , High Speed , Signal Integrity , power-aware SI , SI analysis and modeling , Allegro Sigrity

Verification

Starting Virtual Platform Simulation with Cadence Software Developer

Last time, I provided an introduction to the Eclipse setup for the Cadence Virtual…

• 4 min read
eclipse , Virtual System Platform , Embedded Software Debugging , Incisive

Analog/Custom Design

Virtuosity: 16 Things I Learned in September by Browsing Cadence Online Support

Rapid Adoption Kits By now, I think you know what RAKs are, and that they include…

• 3 min read
custom/analog , Routing , Rapid Adoption Kit , pin placement , Virtuoso Analog Design Environment , Layout , Virtuoso , Analog Design Environment , Schematic Editor , ADE-XL , Virtuosity , Custom IC Design , Virtuoso Layout Suite , VLS XL , Virtuoso Layout Suite XL

Analog/Custom Design

SKILL for the Skilled: How to Shuffle a List

The previous post of SKILL for the Skilled presented some ways to systematically…

• 5 min read
Team SKILL , programming , shuffle , Jim Newton , IC615 , SKILL for the Skilled , permutations , random , Lisp , SKILL++ , SKILL

Verification

Combining the Linux Device Tree and Kernel Image for ARM

Back in 2010, I wrote two articles about a SystemC model used to load the Linux kernel…

• 2 min read
Virtual System Platform , virtual platforms , TLM , ARM kernel image , virtual prototypes , VSP , zimage , boot loader , System Design & Verification , SystemC , Linux device tree , ARM , system-level , linux , Jason Andrews , ESL , kernel

Verification

Getting Started with the Cadence Virtual System Platform: Software Developer

Cadence Software Developer is an exciting Eclipse-based product for developing, debugging…

• 4 min read
eclipse , Virtual System Platform

Verification

Trends in Using Software for System Verification

There is a clear trend to use more software running on the CPUs of a design for system…

• 2 min read
Palladium XP , hybrid engines , linux kernel , Virtual Platforms

Verification

e Macro Debugging

When creating a testbench using the MDV methodology, you want to write intelligent…

• 4 min read
AF , Functional Verification , Debug Performance , e macro debugging , e macros , macro debugging , e language , coverage driven verification (CDV) , macros

Analog/Custom Design

Cadence’s Annual Mixed-Signal Summit 2013: A Mind Meld of Mixed-Signal Design Co…

If you're a fan of the Star Trek series (my six-year-old son and I watch it together…

• 2 min read
IP , cadence , AMS Designer , SV-DC , Incisive , SV-RNM , DMS , Virtuoso , mixed-signal book , mixed-signal summit , RNM , mixed signal

System, PCB, & Package Design 

What's Good About AMS Simulator IBIS Model Capability? It’s in the 16.6 Release!

The 16.6 AMS Simulator now provides IBIS model simulation capability: SPICE circuit…

• 1 min read
PCB , Cadence Design Systems , AMS , Allegro 16.6 , cadence , AMS simulator , IBIS , 16.6 , Capture CIS , Capture-CIS , PSPICE , SPB , design , AMS simulation , Design Entry , Grzenia

System, PCB, & Package Design 

Take Notes During Your Packaging Design Workflow with the Database Diary

In this blog, we take a look, not at a new command, but instead at a classic command…

• 2 min read
IC Packaging and SiP Design , documentation , IC Package , IC Packaging , packaging , Digital SiP design , IC Packaging and SiP , IC package design , APD , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , IC Package Physical layout and co-design

Verification

Slow Winter or New Spring for Hardware Design?

If you're looking for an entertaining gonzo take on the history and current state…

• 4 min read
5G , algorithms , microsoft , H.265 , James Mickens , process scaling , Hardware design , HEVC , 4K , Apple M7 , Moto X , high level synthesis , Adreno 320 , System Design and Verification

System, PCB, & Package Design 

What's Good About Capture’s Update Cache? 16.6 Has a Few Enhancements!

The 16.6 OrCad Capture release now allows you to replace multiple cache parts in…

• 1 min read
PCB , capture , Cadence Design Systems , Allegro Design Entry , Allegro 16.6 , Design Entry CIS , cadence , OrCAD Capture , 16.6 , Capture CIS , Capture-CIS , SPB , OrCAD , PCB design , Design Entry , Grzenia , Allegro

SoC and IP

TSMC 28HPM – Sweet Spot for Today’s Mobile SoCs

Mobile is the only business besides PCs where actual SoCs get a lot of visibility…

• 2 min read
cadence , Jacek Duda , MIPI , M-PCIe , USB , future of IP , USB3.0 , Qualcomm , SuperSpeed USB Inter-Chip , SSIC , 2013

SoC and IP

Automotive Ethernet Interest Soars at Industry Events

I attended two consecutive automotive Ethernet events near Stuttgart last week. Judging…

• 2 min read
controller IP , 802.3bp , Design IP , cadence , controller , OPEN Alliance , Automotive Ethernet , IEEE 802.3 , broadcom , Ethernet , Marris , Ethernet PHYs , BMW

System, PCB, & Package Design 

Customer Support Recommended - Dimensioning in Allegro PCB Editor

Allegro PCB Editor offers drafting and dimensioning features that support electronic…

• 3 min read

System, PCB, & Package Design 

What's Good About ADW’s Pull-Down Lists? 16.6 Has a Few New Enhancements!

The 16.6 Allegro Design Workbench (ADW) release now provides the ability to customize…

• 2 min read
Cadence Design Systems , Allegro 16.6 , cadence , DBeditor , 16.6 , property , Allegro Design Workbench , Library flow , selection filters , Library and design data management , SPB , design data management , Front-end PCB design , design , PCB design , Design Entry , Grzenia , Librarians , library , ADW , Allegro

SoC and IP

Intel Developer Forum (IDF13): A "Look Inside" the Technology Showcase

The recent Intel Developer Forum 2013 in San Francisco was notable for the sheer…

• 3 min read
Intel , IDF13 , Design IP , IP , Rajkumar Chandrashekhar , Gen3 , cadence , Intel Developer Forum , MIPI , M-PCIe , Arif Khan , MPCIe , Mahesh Wagh , PCIe , interoperability , PCI Express
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