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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
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Blog - Post List

Latest blogs

Artificial Intelligence (AI)

Renesas Collaborates on Large Language Model Generative AI Chip Design

Renesas and Cadence have been collaborating for several years, combining their expertise…

• 2 min read
featured , LLM , cadence.ai , cerebrus , Renesas

Academic Network

Academic and Entrepreneur Tracks at CadenceLIVE Europe 2023

I am very happy to announce that registration for the in-person CadenceLIVE Europe…

• 3 min read
Student Design Teams , Master Thesis Award , Proof-of-Concept , Academic Track , CadenceLive Europe

Analog/Custom Design

How Much Do You Know About Virtuoso Studio?

How much do you know about Virtuoso Studio? Here are the answers to the True or False…

• 5 min read
featured , Virtuoso , analog design , Custom IC

Verification

Verification of Integrity and Data Encryption (IDE) for CXL Devices

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe…

• 3 min read

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre FMC Analysisのご紹介

プロセスが微細化するにつれて、デバイスのミスマッチが回路性能に与える影響は大きくなり、現在では、このミスマッチが性能指標に与える影響を解析するために、さらに多くのモンテカルロ…

• 1 min read
Spectre Circuit Simulator , Monte Carlo analysis , Spectre Fast Monte Carlo , japanese blog , Virtuoso ADE Assembler , ADE Assembler

Learning and Support

From Learners to Innovators: Inside Cadence’s Certified Training Partner Program

The news is replete with stories of a global shortage of engineers, which is only…

• 2 min read
coverage , debug , Signoff Timing and Power Analysis , Cadence training , Cadence certified , Training Partners , Languages and Methodologies , simulation , Digital Physical Design , Synthesis and Static Timing Analysis

定制IC芯片设计

Virtuosity: Virtuoso Design Intent支持多语言注释

ICADVM20.1 ISR20 开始，用户可以使用普通话、日语、印度语等非拉丁字符的语言来编写 Design Intent 中的注释。

• less than a min read

Computational Fluid Dynamics

Automatically Generate the Best Mesh Each Time with Adaptive Grid Refinement

The goal of simulation preprocessing is to create a mesh that is suitable for the…

• 5 min read
Computational Fluid Dynamics , simulation software , Mesh Generation , Cadence CFD , Adaptive Grid Refinement , Fidelity Pointwise

Digital Design

Training Webinar: A Revolutionary Approach to Optimizing Chip Design

Please join me, Cadence Training and Application Engineer Krishna Atreya, for this…

FormerMember • 1 min read

Analog/Custom Design

Start Your Engines: Use Tcl to Save Signals More Efficiently in AMS Simulations

For large SoC designs, the simulation performance might get impacted by the number…

• 3 min read
save statement , AMS , AMS Designer , AMSD , Start Your Engines , Spectre AMS Designer , Mixed-Signal , probe , xcelium

Artificial Intelligence (AI)

Cadence CEO Unveils Exciting LLM GenAI Breakthrough for Chip Design

In a recent keynote address, Dr. Anirudh Devgan, president and CEO of Cadence, shared…

• 3 min read
artificial intelligence , featured , LLM , cadence.ai , GenAI , AI

Corporate News

INEOS Britannia Is Designing for the Next America's Cup with Cadence

As teams gear up for the 37th edition of the America's Cup, the pressure is on to…

• 1 min read
CFD , FINE Marine , designed with cadence , Computational Fluid Dynamics , america's cup

Verification

The Crucial Need for Synchronization with Third-Party Systems

In today’s interconnected world, businesses and organizations rely heavily on various…

• 3 min read

System, PCB, & Package Design 

Training Webinar: Celsius Thermal Solver - Recording Available

The Cadence Celsius Thermal Solver is the industry’s first complete electrothermal…

• 1 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , PDN , Signal Intregrity , Power Integrity , PCB Signal integrity , PCB design , PowerDC

Corporate News

Cadence Creates Industry’s First LLM Technology for Chip Design

In the nine short months since OpenAI brought ChatGPT (a Chat Generative Pre-Trained…

• 4 min read
featured , LLM , cadence.ai , Generative AI , GenAI

Artificial Intelligence (AI)

Common Tensilica Software Stack Delivers Best-In-Class Edge AI Performance

Developing an agile software stack is important for successful AI deployment on the…

• 2 min read
artificial intelligence , Edge AI , featured , deep learning , ai-driven , On-Device AI , AI/ML

PCB、IC封装：设计与仿真分析

如何在封装设计中创建并使用非圆形过孔堆叠？

要设计出尺寸更小的电子器件，可以在多层基板或多层印刷电路板 (PCB) 中采用高密度设计，增加每层的使用率。在多层封装或多层电路板的设计和制造过程中，过孔的作用不可或缺…

• less than a min read
Chinese blog , IC封装设计 , 软件技巧 , Allegro Package Designer Plus , 中文 , Allegro

System, PCB, & Package Design 

CadenceTECHTALK: Solution for 3D-IC Interposer Signal Integrity

3D-IC design requires early analysis of thermal properties, power delivery, and signal…

• less than a min read
3D-IC , Signal Integrity , interposer

Spotlight Taiwan

CadenceLIVE Taiwan 2023 感謝有您、圓滿落幕!

半導體與 EDA年度盛會 - CadenceLIVE Taiwan 使用者大會在8月31日圓滿落幕。匯聚超過40場技術趨勢演講、涵括 6大技術分場與成功案例、串聯近20家產業學界專家…

• less than a min read
MSA , 3D-IC , cadencelive taiwan , Virtuoso , taiwanese blog , intelligent system design
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